NOTE: Please note that the tutorial does not show that you must select “Gadget Factory Papilio Custom Board” under tools/board in the Arduino IDE for the simulation file to be generated.
This screencast shows how to simulate a custom user core connected to the AVR8 Soft Processor. Simulation is the most efficient way to debug your custom VHDL or Verilog code or to learn about the AVR8 internals.
Follow along as we debug a custom core that extends the functionality of the AVR8 Soft Processor. We dig into the AVR8′s program counter, opcodes, and external pins as we delve into the internals of the soft processor.
- AVR8 Source Code
- Arduino IDE modified for the Papilio.
- Xilinx ISE free “Webpack” version.
- Custom User Core sketch.
- Modify the Arduino Makefile to enable Simulation (2:00)
- Load and modify custom user core sketch. (3:05)
- Compile sketch with verbose output. (4:30)
Read the entire article for Videos 2-5.
- Verify that simulation VHDL file was created. (0:05)
- Understand what the sketch is going to do. (0:36)
- Disassemble the Arduino sketch. (1:10)
- Open AVR8 for simulation in Xilinx ISE. (3:20)
- Enable AVR8 custom user core. (4:05)
- Change to simulation view and load testbench. (0:01)
- Generate your own testbench if there is not already one defined. (0:58)
- Start simulation in ISIM. (2:39)
- Add and group signals from external, custom core, and AVR8 core. (3:40)
- Add and group signals from external, custom core, and AVR8 core continued. (0:00)
- Run simulation for 3ms. (0:36)
- Find our interesting events in the waveform view. (0:50)
- Find the program counter and instruction bus. (1:34)
- Match program counter from disassembly with location in simulation. (1:53)
- Verify that actions that occur at our program counter match what we expect from the disassembly. (3:02)
- Verify that actions that occur at our program counter match what we expect from the disassembly continued. (0:00)
- Wrapup, conclusions, and advice on what to look for when simulation works but synthesis does not. (3:15)