Cx: A New Language for Hardware Design & Verification

November 25th, 2014

Here is another new language for high level hardware description. We haven’t used it but this article has a clear description of why a hardware description language that goes further then VHDL or Verilog is needed.


Cx (formerly C~) is a new language for hardware design and verification that is at an intermediate level of abstraction between RTL and HLS. Why is a new language necessary? Because most hardware designers are still stuck with RTL, and because today’s High-Level Synthesis (HLS) does not live up to its promises. Register Transfer Level (RTL) is pretty self-explanatory — you think in terms of registers and how data flows from one register to the next. This closely matches what happens physically, which is another way of saying that it is a very thin layer of abstraction. In turn, this means that you spend a lot of time dealing with implementation-level details that would not concern you if you were working at a higher level of abstraction. VHDL and Verilog are the two main historical languages for describing RTL designs. Both date back to the 1980s and — in the grand scheme of things — have seen little evolution since then. Recent efforts to improve on these two relics include open-source initiatives like MyHDL (RTL in Python) and Chisel (RTL in Scala). MyHDL is led by Jan Decaluwe, while Chisel was created at UC Berkeley with the goal of facilitating processor design. At the other end of the spectrum, we have HLS. We can think of today’s HLS as your manager’s solution. It was sold to her or him (at a premium) as a way to increase productivity and obtain the same performance as RTL. The problem is that [...]



First Impression on the ESP8266 Serial-to-WiFi Module

November 18th, 2014

Very nice writeup of using the ESP8266 $5 WIFI module.


What is Serial-to-WiFi? Simply put, it means using serial TX/RX to send and receive Ethernet buffers, and similarly, using serial commands to query and change configurations of the WiFi module. This is quite convenient as it only requires two wires (TX/RX) to communicate between a microcontroller and WiFi, but more importantly, it offloads WiFi-related tasks to the module, allowing the microcontroller code to be very light-weighted.

SmartMatrix Animated GIF Player

November 13th, 2014

Nice guide and library for playing animated GIFs on those RGB LED Array’s. We should be able to port this library to the ZPUino for use with the RGB LED Wing.

This guide will show you how to add a microSD card to a Teensy 3.1 to play back animated GIFs on a 32×32 Pixel RGB LED Matrix Panel.  The Teensy 3.1 runs an Arduino sketch that decodes the animated GIF and refreshes the display at a high frame rate with good color depth.  The SmartMatrix Shield makes it easy to connect everything together. We will explain the basic soldering and wiring to connect the microSD card reader to the SmartMatrix Shield, how to compile the Arduino sketch that decodes the GIF animations, and go over options for creating your own GIFs. Bare panel on the left, mounted in an 8″x8″ shadow box frame with frosted acrylic diffuser on the right. Major Components 32×32 RGB LED Matrix Panel A 32×32 RGB LED Matrix Panel is an affordable way to add over a thousand bright pixels to your project.  Compared to a Neopixel matrix, these panels use smaller LEDs which are bright but not as blinding, and have a higher pixel density.  Unlike a Neopixel matrix, the panel requires a microcontroller to refresh the LEDs continuously to display an image.  It takes about 40% of the CPU time and most of the memory of an Arduino Uno just to refresh a panel, and that’s with a low refresh rate and a limited 12-bit color palette.  To get a better image quality, we will use a more powerful microcontroller. Teensy 3.1 Despite its small size, the Teensy 3.1 packs a lot of horsepower as it uses [...]

An SDK for the ESP8266 WiFi Chip

November 12th, 2014

There is an SDK for the $5 ESP8266 WIFI module now!












The ESP8266 is a chip that turned a lot of heads recently, stuffing a WiFi radio, TCP/IP stack, and all the required bits to get a microcontroller on the Internet into a tiny, $5 module. It’s an interesting chip, not only because it’s a UART to WiFi module, allowing nearly anything to get on the Internet for $5, but because there’s a user-programmable microcontroller in this board. If only we had an SDK or a few libraries… The ESP8266 SDK is finally here . A complete SDK for the ESP8266 was just posted to the Expressif forums, along with a VirtualBox image with Ubuntu that includes GCC for the LX106 core used in this module. Included in the SDK are sources for an SSL, JSON, and lwIP library, making this a solution for pretty much everything you would need to do with an Internet of Things thing. As far as LX106 core is concerned, there’s example code for using the spare pins on this board as GPIOs, I2C and SPI busses, and a UART. This turns the ESP8266 into something much better than a UART to WiFi module; now you can create a Internet of Things thing with just $5 in hardware. We’d love to see some examples, so put those up on  and send them in to the tip line….


DIY LED Video Cube

November 11th, 2014

Now this is sick! Can we make it better with the Papilio FPGA?

JAMES DEVITO After finishing the LED Video Wall , I wanted to take advantage of the fact that each panel is modular and can be arranged in nearly any way imaginable. I present to you, the Adafruit Video Cube! Each side has 1024 LEDs, for a grand total of 6144 LEDs– it’s super bright in every direction! It works nearly identical to the LED Video Wall in that the video decoder boards do all the hard work – All you need is a DVI/HDMI/Displayport output with the proper cable, a good 5V power supply and a little wiring time. The driver supports up to 1024×800 displays. Once programmed and configured you can use any video source! This is not a beginner project! It is strongly recommended to start out with our LED Video Wall before embarking on this adventure! Because so much has to fit inside the cube, it requires some modifications that could potentially damage the hardware if you are not careful and patient! There’s also a lot of wiring and power management. We don’t sell all the components required so you may need to spend some time getting all the parts you need. Building the cube can take a few weekends and requires care and patience. Here at Adafruit we love this kind of thing, and we have documented the process as best as possible but there’s not a lot of documentation out there about these systems so even though we got our cube working nicely [...]


November 6th, 2014

Here is another great Xilinx App Note that sheds light on Digital Clock Managers available for Spartan 3 and 6 chips.


Digital Clock Managers (DCMs) provide advanced clocking capabilities to Spartan™-3 FPGA applications. DCMs optionally multiply or divide the incoming clock frequency to synthesize a new clock frequency. DCMs also eliminate clock skew, thereby improving system performance. Similarly, a DCM optionally phase shifts the clock output to delay the incoming clock by a fraction of the clock period. The DCMs integrate directly with the FPGA’s global low-skew clock distribution network.

Great news! Papilio DUO, Computing Shield, and LogicStart Shield going into production at Seeed Studio!

November 4th, 2014


Great news, I just made payment to Seeed Studio to start manufacturing the first batch of boards! They expect to easily meet the December delivery time frame and may even have them completed in November. :) We had a bit of a scare and a last minute scramble due to a global shortage of ATmega32U4 chips in the QFN package. We were actually ready to start manufacturing the boards at the beginning of October but were unable to find ATmega32U4 chips in any of the normal distribution channels! Digikey reported that chips should be back in stock on November 5th, which would be enough time manufacture the Papilio DUO by December. But, it has been my experience that you can’t trust those estimated stock dates, if that date were to slip at all we would not be able to deliver the Papilio DUO in December. So Seeed Studio and I sprang into action after discovering that there was quite a bit of stock of the ATmega32U4 chip in the TQFP footprint available. I quickly made a new revision of the Papilio DUO board that has both the QFN and TQFP footprint and Seeed Studio was kind enough to rush the updated design through their prototyping service. They already have all of the parts lined up and are now doing the final tests with the prototype, as soon as it passes they will put the DUO on their production line.  Here are pictures of the prototypes [...]




Guide for Generating ROMs and BRAM Memory

October 30th, 2014

Hamster tipped us off to this nice guide about generating memories with the Xilinx wizards.

The objective of this lab is to illustrate the use of ROM and block RAM memories located inside the FPGA – a Spartan-6 in the case of our Atlys board. We’ll learn how to use the ISE’s Core Generator tool to create BRAMs. Depending on what your course project will do, you may need to use such memories in your project.

Screen Shot 2014-10-31 at 8.56.53 AM

The contents of these memories will be read continuously and displayed on the 7 LEDs. Slide switch SW(0) is used to select between the two outputs of the two memories to drive the LEDs. A simplified representation of this functionality is shown in the block diagram in Fig.1.