The most obvious factor when choosing an oscilliscope is bandwidth. 50MHz is better than 20MHz, and 100MHz is definitely better than 50MHz, etc., but what does that number really mean, and how fast is fast enough for your needs? There are already some good resources out there that go into exhaustive details on this … but for the executive summary read on.
The brains of the outfit is a $5, 100-pin CPLD from Xilinx. Apart from that, the rest of the components are a crystal, PLL, and an almost hilarious number of resistors for the R2R ladder. The one especially unique component is the 25.056815 MHz crystal – multiply by that by two, and it’s fast enough to drive a VGA monitor. Divide the crystal by seven, it’s the 3.579545 MHz you need for an NTSC colorburst frequency. That’s VGA and NTSC in a single programmable logic project, something the one FPGA project we could find that did color NTSC couldn’t manage.
Anyway, one result is an ADC demo that got out of necessity a little more polished than planned.
- Controls LED brightness with input 1 (the one closest to the SD card). The signal pin faces the edge of the board.
- Dumps all 16 channels through USB. Set up virtual com port for the 2nd USB interface, open Teraterm and connect with default settings (9600 baud, 8 bits, 1 stop bit)
- There is some information out there regarding control of this ADC that I find questionable, after reading the data sheet (It states explicitly that there are no timing requirements between falling edges of CS and CLK so they may change in the same cycle and the whole control logic simplifies greatly)
- ADCs run at 50 % of maximum throughput, that is, they take turns. 8 frames are captured in one shot.
- The data sheet shows 10 bits even though it’s an 8-bit ADC. The implementation picks the correct ones, others are apparently zero (edit: no they are not – you get 10 bits of data out of the ADC)
Hamster shows us how to use the latest and greatest WS2812B LEDs!
The interface is pretty simple – the state of the bus has to be reset by holding the data signal low for 50us, followed with sending out 24 bits for each LED that is connected in the string. The ’1′ bits are sent by driving the data line high for 0.9us, followed by driving the line low for 0.35ns, The ’0′ bits are sent by driving the line high for 0.35us, then driving it low for 0.90us. The frame is in 8-bit Green, 8-bit Red then 8-bit Blue format, and within each colour the MSB is sent first.
We( Haolin and Joris ) built this oscilloscope last semester for a school project. The ADC chosen is a high performance differential ADC which uses Low-voltage differential signaling (LVDS). A FPGA is used to interface the ADC accounting for its properties such as high clock frequency, parallelism and differential inputs/outputs. The back-end software is written in QT with OpenGL libraries. This software supports oscilloscope and FFT functions.
Colin O’Flynn makes a cool video showing the ZAP IDE in action! Watch as he makes a custom PWM peripheral, adds it into the ZPUino Soft Processor, and writes C code to control it.
Jump to 37:10 mark to see it working! Full details at http://programmablelogicinpractice.com in August 2014 Issue of Circuit Cellar. Code is located as a link on that blog post.
More pictures of Jack Gassett visiting a PCB factory in Shanghai with Jingfeng of Linksprite:
Here are more pictures from a lake in Beijing:
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