Very few know how Powerful this FPGA combination can be – Here is how to Control it

August 8th, 2016

Greetings inhabitants of the FPGA world! Today’s post is about a project that can be a huge part of a number of other different projects that use FPGA as their core. Be it a claw machine or a drone or a navigator robot, interfacing Joysticks with FPGA will be a fundamental part of many of your future work. This article will help you control any device on a two dimensional platform with the code for movement in the XY plane. Moving in 3D (flight in the case of drones) can be easily achieved by using two joysticks in place of one.

The Author has wrapped up her project in a set of 5 steps to keep things short and sweet. The hardware needed for this project is simply a FPGA board, a system with Xilinx Vivado installed, Digilent PmodJSTK and a USB A to B micro cable. A general idea regarding the project is given in Step 2. The Joystick uses the SPI interface to receive and transmit data from and to the FPGA board.

The code for this project has been readily supplied in step 3 as a zip file. The contents can be sorted into a number of modules which have been coded in Vivado 2015.4. So using a different version of the software will mean you need to copy paste the codes into a new project file in your system.

The code can then be converted to bit stream to programme the board. You can also programme 2 joysticks (for Drones or RC Cars) since only the top bank of the PMOD Header in the FPGA board (you may need to adapt this to your own board) has been used for 1 joystick.


By Commanderfranz

The Daredevil Cam is Closer to Those with this Info and a FPGA

August 4th, 2016


Hello FPGA hobbyists! Ever wondered what it would be like to see sound? The author thveryat very same curiosity for close to 10 years, and kept a constant vigilance for ideas to build something that would help him materialize his dreams. The Daredevil camera, built using a bunch of MEMS microphones and a FPGA actually lets you see sound.
The author started the project wielding inspiration from the Duga RADAR. However, the scale of the project becomes huge and something beyond what hobbyists can afford. The author then tried a more practical but tedious and time consuming design approach which involved using an array of microphones. Each microphone in the array picks the sound relative to its position and displays it on screen, which will always be different from the next microphone because of the difference in position.
While the logic behind this is sound, implementing an array of microphones, each having a Pre-amp stage and then an ADC stage before feeding inputs to the FPGA is not practical. The cost and time put into the project becomes huge, and even then error margins can be significantly high.
This is the reason why the author used a set of MEMS microphones. MEMS microphones have an inbuilt Pre-amp and ADC stage, and thus the project collapses in complexity. All that is needed is an array of MEMS microphones and an FPGA board to implement the project. FPGAs are FFT friendly and this has a huge part in the project.
The author has shared the PCB design layout here. Besides this a number of fail safes such as spare patterns for a Flash chip, SOIC and DIP. He also used micro SD cards for each array to store the data and send it for processing to get an output of close to 30 frames per second. The FPGA, a great tool for pipelining is used to get his output.
The author then tried out the theory in an 8×8 array and arrived at the conclusions that the device is pretty sensitive as it even picks up sound way reflections from surfaces. But since anechoic chambers are impossible to build at home, he went on to build a 16×16 array.
While the results can be seen in this page, the author is yet to perfect his design. There are persistent issues with micro SD card since its storage algorithm conveniently cuts off data to compress data, which is essential for the FPGA to build a 30 Frame/sec output.
To be heard…or seen.


By Artem Litvinovich

How to Make a Cleaner Planet with Your FPGA

August 2nd, 2016

Greetings FPGA fans! Today’s post takes power generation and conservation to another level! We all know that Solar Panels are an excellent source of non-conventional power. But if the panel is not facing the sun the power generation is never optimum. The sun changes its position continuously and a static solar panel can only generate optimum power for a short window of time when it directly faces the sun. But what if the solar panel too changed its position with respect to the sun? Then we would have a case where the panel generates optimum power for more than 8 hours which is a lot more compared to just the 1-2 hours it does when it is static!

Today’s project aims at making a dynamic solar panel with FPGA. This Dynamic Solar Panel changes its position according to the Sun’s position by making use of a comparator that compares voltage values periodically and rotates the panel. The hardware required for this project are 2 Bidirectional Parallax servo motors, a 9V DC Solar Panel, a FPGA, a Breadboard, A 3D Printed frame and 3 100 Ohm resistors.

The Project basically involves the use of an FSM designed by the author. The design steps have been explained in detail from steps 2 – 8. Any FPGA with sufficient inputs and outputs can be used for this project but the code shared by the author has been programmed for the Basys 3. So unless you’re feeling really adventurous, it would be best to follow what the author has done!

The program has been done in VHDL (.vhd) and is available here. It has been arranged into different modules and each module corresponds to one of the design steps from 2 – 8. The program is pretty easy to follow and improvising it to suit another FPGA board should be easy if you know VHDL.

The wiring has been shared in step 10. The author has used a 3D printed frame whose schematic has been shared in step 11. However if you plan on building your own frame from wood or cardboard, you can refer the sketches.

Let’ build a cleaner planet having fun!

By nickthequik

Build your own Mandelbrot Fractal Generator with FPGA

July 14th, 2016

Greetings FPGA lovers! Today’s post takes you into yet another interdisciplinary project that links pure mathematics, FPGA and VHDL to build something beautiful! The Mandelbrot set is a series of complex numbers that tend to infinity when operated upon by a special operator. These numbers when grouped together create a beautiful image sequence which might appear to be chaotic initially. But simplifying the set, we soon find that Mandelbrot’s numbers are nothing but fractals and this concept can be explored and understood visually with FPGA and VHDL.

Today’s project is an FPGA based Fractal explorer that has been built out of the Papilo Duo kit which includes Xilinx Spartan 6 LX9 FPGA, an ATmega 32U4 microcontroller and a 512 MB Static RAM. Some other hardware needed is a basic 7” LCD screen, a Joystick, a few buttons and a rotary encoder.

The colour map shown in the project is navigated by using the joystick to move around, rotary knob to chose colour scheme and the buttons to zoom in and out. These controls are connected to the ATmega 32U4 microcontroller which is interfaced with the FPGA through an SPI interface.

The LCD has been tweaked to display 800 x 600 and the FPGA has also been correspondingly set to process 800 x 600 pixel fractals using the inbuilt DSP 48s. The project is inspired by the Mandelbrot Fractal Generator by Hamster.

Though the code for this project is still unavailable at the moment, you can refer Hamster’s project to get the basic dataflow and code in the C language. Once you do have the logic at hand, the project can easily be converted to the FPGA/VHDL combination instead of the Computer/C combination used by Hamster.

The project is an excellent way to continue learning coding through VHDL and get used to the Papilo Duo Kit.


By Larry McGovern

Recreating Nintendo Chiptunes with FPGA and the 6502 processor

July 12th, 2016

Greetings FPGA lovers! Today’s project explores the possibility of using FPGA in combination with other processors to recreate the amazing Nintendo Chiptunes or Soundtracks that an entire generation of gamers are used to. The project uses a combination of FPGA with Verilog and the 6502 processor along with a Nesdev APU for audio generation.

The Hardware required for the project consists of the NIOS II FPGA, 6502 processor, Nesdev APU, SD card reader and a few other components needed to create the three primary blocks which are the timer block, length counter block and an envelope unit. These 3 blocks use a network of Mixers and PIOs besides the 5 channels available on the APU.

Out of the 5 channels available on the APU, only 4 channels have been used by the developers since the fifth channel (Delta Modulation Channel) is a time consuming endeavour. However the project does successfully emulate perfect chiptunes with the hardware. A detailed explanation of the Hardware used can be found here.

The coding used for this project is a combination of Verilog and C since FPGA and the 6502 are used. The Verilog Coding is used to extract Nintendo Sound Format files (.nsf) from the SD card reader onto the FPGA. The NSF files can be loaded on to the FPGA through the 6502 processor which has been coded in the C language using standard functions. NSF files can be stored on the SD card using a computer.

The NIOS II FPGA acts as an NSF player in this particular project.  It can be used to control playback, stop tracks or forward and rewind to the next or previous track.

Using just 4 channels in the APU the developers have done an amazing job and an example of the fruits of their labour (and an inspiration!) can be seen here.


By A. Heil and S. Zhao

Process VGA without Frame Buffers using FPGA

July 7th, 2016

Hello explorers of the FPGA Kingdom! Today’s project digs into the scope of FPGA as a tool that can replace conventional techniques further. VGA or video processing through conventional means requires a frame buffer which stores a block of data regarding pixel information in the system RAM for video display which is transferred to the display device at the right time using real time means. FPGAs can replace these frame buffers in a novel way such that the system RAM utilized for this remains free at the cost of a little more real time computation.

The developers used a DE2-115 FPGA board along with a Wolfson Audio Codec to animate 4 characters on the screen such that they appear to be dancing to the beats of the music played. Apart from those hardware elements, a monitor (graphics module) was used.

The coding was done by the developers using MATLAB since the project requires the use of filters through DFT and MATLAB has functions readily available for this. THE DFT is used to filter out the lowest frequency component (which will be the percussions or beats) and then calculate the interval at which this repeats. Once this information is obtained, the music is passed on from the ADC of the Codec to the monitor through the FPGA for animation.

The graphics on screen are programmed in modules such as a “head” file, a “body” file, an “arms” file, and a “legs” file which induce movements to the body parts depending upon the information processed by the FPGA from the rhythm of the music played. For a detailed explanation regarding the project, design, testing and systems integration you can visit the developers’ page here.

The result of this project can be seen here.

Though the project is not a replacement to the fast and efficient way of processing VGA through Frame buffers, it certainly explores the academic value and versatility of the FPGA as a tool that can be used for multiple purposes.

By C. Archard and N. Levy

Critical Tips to Build Your Own C88 Homebrew Computer with FPGA

June 30th, 2016

Greetings FPGA lovers! Today’s post is about building your own mini computer using FPGA. The project has been inspired by the first SSEM, popularly called the Manchester baby. The project resembles its inspiration in certain aspects, but being a homemade CPU with minimal components and coding, the specs are not as formidable as the SSEM.

The author has used a standard FPGA Papilo one 500k board, an 8×8 LED strip and a set of switches. The system has been designed for a total RAM of 64 bits, and the LED strip shows the RAM configuration every time data is entered at a new address. Besides this, the author has also used a rechargeable battery, charging circuit, clipper circuit to avoid excess voltage and a number of peripheral ICs.

The coding followed for FPGA is based on simple VHDL (.vhd) and being an open source project, the author has shared all VHDL code here. The CPU is programmed directly using the address and data switches. A number of values can be stored just by setting the CPU on the User mode and entering data to the addresses of the 64 bit RAM.

The system also has an adjustable clock which helps while simulating and running the code in variable clock speeds. The author has successfully demonstrated through the video that the CPU can work as a Random number Generator (from 1 to 6) and a pendulum. Besides this the CPU can also be connected to external components like an array of LEDs for clarity of output.

Though the FPGA based C88 Homebrew CPU has limited RAM and storage capabilities, it is still a great start to create experimental modules and platforms using FPGA that can host a number of applications.

Have Fun!


By Daniel Bailey

[DIY] How to Make a FPGA-based Electric Composer

June 28th, 2016


Hello FPGA enthusiasts! Today’s project takes sound production using FPGA to another level. The project under focus is building an electric keyboard/composer using FPGA. The keyboard acts as a song tune composer where a network of switches on the FPGA board is connected in precedence such that while a switch is on, the corresponding note plays.

The major hardware components needed are just a FPGA board (you may need  to adapt this project to your own board), a speaker capable of playing a wide range of frequencies, and not just a monotone, and an auxiliary cable or suitable wires for connecting the speaker to the FPGA board.

The coding has been done using Xilinx ISE in the VHDL (.vhd). The author has given a detailed pin assignment as well as a basic VHDL background explanation. The code has been shared from step 5 to 9 and each module has been well explained by the author. The modules basically consist of a frequency division for playing different frequencies of sound and process statements for fixing parameters like precedence and sensitivity.

Setting the port map and executing the program has been explained in steps 10 and 11. By switching different switches you get different tones, though combinational tones cannot be made since precedence is followed.

The show must go on!

By krosenfeld7