At Maker Faire Lisbon: ZPUino

September 4th, 2014

Our good friend Alvaro Lopes is going to be at the Lisbon Maker Faire from the 19th – 21st of September 2014. So if you are in the area be sure to stop by the ZPUino booth and say hello!

ZPUino is a SoC (System on a Chip) developed by Álvaro Lopes , a senior engineer from Critical Software in Coimbra and a blogger at the EE Times . It’s a 32 bits, 100Mhz CPU implemented in a FPGA , and programmed using the Arduino tools and a specific schematics editor for the hardware parts (internal peripherals). At the Lisbon Maker Faire he’s going to demonstrate the system and its connection to more complex hardware. He will be using 9 different FPGA boards, lots of peripherals, RGB LED panels and strips, HDMI output video (with a monitor), Audio (directly from the FPGA with an audio codec). You will see games, interactive applications, and other. The ZPUino has been used in projects like the Soundpuddle , the RetroCade Synth , and others . We specially like its use in the Papilio Arcade MegaWing : We can’t wait! Comments comments powered by Disqus

link in Portuguese

Welcome to the online home of The Zynq Book

September 3rd, 2014

Image of the Zynq BookCurious about the Xilinx ZYNQ processor – an FPGA core coupled with two ARM hard processors? Take a look at this free eBook released by Xilinx to learn more!

The Zynq Book is the first book about Zynq to be written in the English language. It has been produced by a team of authors from the University of Strathclyde, Glasgow, UK, with the support of Xilinx. We wanted to create an accessible, readable book that would benefit people just starting out with Zynq, and engineers already working with Zynq. We hope that it will prove a handy reference that remains on your desktop! You can find out more about the book’s contents on the About page.

Flavia: the Free Logic Array

August 27th, 2014

Flavia: the Free Logic ArrayCheck out this amazing project from John Beetem. Make small Digital Logic designs without the heavyweight vendor tools. Flavia tool chain lets you make bit files for the Papilio One 250K with completely FLOSS software! Only CPLD sized designs are possible, but this is a boon for learning Digital Logic on ARM based boards like the Raspberry Pi.

Abstract: Flavia is a family of logic arrays that can be designed and programmed entirely using free-as-in-freedom (FaiF) software.  This is in contrast to standard FPGA (Field-Programmable Gate Array) tools from vendors such as Xilinx, Altera, Lattice, Cypress, and MicroSemi (formerly Actel) where you must use the vendor’s software to design the FPGA.  Except for a part from Atmel that never caught on, the author is not aware of any commercial FPGA or CPLD (Complex Programmable Logic Device) that can be designed without running its vendor’s tools.

Papilio DUO Pre-Orders Now Available On Backerkit

August 25th, 2014

Papilio DUO

Great news! Papilio DUO pre-orders are finally here , we are using Backerkit to take pre-orders and we are offering so many exciting add-ons with some good discounts.

Please visit the pre-orders page here to take advantage from these discounts and make sure you get your Papilio DUO board as soon as we get them in stock.


Why Oscilloscope Bandwidth Matters

August 8th, 2014

This is a great article about why Oscilloscope Bandwidth matters. If you are looking to buy a new Oscope soon then give this a read. Thanks Adafruit!

The most obvious factor when choosing an oscilliscope is bandwidth. 50MHz is better than 20MHz, and 100MHz is definitely better than 50MHz, etc., but what does that number really mean, and how fast is fast enough for your needs? There are already some good resources out there that go into exhaustive details on this … but for the executive summary read on.

A CPLD Video Card With VGA And NTSC

August 7th, 2014

NTSCHere is a project to generate VGA and NTSC from a CPLD.

The brains of the outfit is a $5, 100-pin CPLD from Xilinx. Apart from that, the rest of the components are a crystal, PLL, and an almost hilarious number of resistors for the R2R ladder. The one especially unique component is the 25.056815 MHz crystal – multiply by that by two, and it’s fast enough to drive a VGA monitor. Divide the crystal by seven, it’s the 3.579545 MHz you need for an NTSC colorburst frequency. That’s VGA and NTSC in a single programmable logic project, something the one FPGA project we could find that did color NTSC couldn’t manage.