July 14th, 2016
Greetings FPGA lovers! Today’s post takes you into yet another interdisciplinary project that links pure mathematics, FPGA and VHDL to build something beautiful! The Mandelbrot set is a series of complex numbers that tend to infinity when operated upon by a special operator. These numbers when grouped together create a beautiful image sequence which might appear to be chaotic initially. But simplifying the set, we soon find that Mandelbrot’s numbers are nothing but fractals and this concept can be explored and understood visually with FPGA and VHDL.
Today’s project is an FPGA based Fractal explorer that has been built out of the Papilo Duo kit which includes Xilinx Spartan 6 LX9 FPGA, an ATmega 32U4 microcontroller and a 512 MB Static RAM. Some other hardware needed is a basic 7” LCD screen, a Joystick, a few buttons and a rotary encoder.
The colour map shown in the project is navigated by using the joystick to move around, rotary knob to chose colour scheme and the buttons to zoom in and out. These controls are connected to the ATmega 32U4 microcontroller which is interfaced with the FPGA through an SPI interface.
The LCD has been tweaked to display 800 x 600 and the FPGA has also been correspondingly set to process 800 x 600 pixel fractals using the inbuilt DSP 48s. The project is inspired by the Mandelbrot Fractal Generator by Hamster.
Though the code for this project is still unavailable at the moment, you can refer Hamster’s project to get the basic dataflow and code in the C language. Once you do have the logic at hand, the project can easily be converted to the FPGA/VHDL combination instead of the Computer/C combination used by Hamster.
The project is an excellent way to continue learning coding through VHDL and get used to the Papilo Duo Kit.
By Larry McGovern
July 12th, 2016
Greetings FPGA lovers! Today’s project explores the possibility of using FPGA in combination with other processors to recreate the amazing Nintendo Chiptunes or Soundtracks that an entire generation of gamers are used to. The project uses a combination of FPGA with Verilog and the 6502 processor along with a Nesdev APU for audio generation.
The Hardware required for the project consists of the NIOS II FPGA, 6502 processor, Nesdev APU, SD card reader and a few other components needed to create the three primary blocks which are the timer block, length counter block and an envelope unit. These 3 blocks use a network of Mixers and PIOs besides the 5 channels available on the APU.
Out of the 5 channels available on the APU, only 4 channels have been used by the developers since the fifth channel (Delta Modulation Channel) is a time consuming endeavour. However the project does successfully emulate perfect chiptunes with the hardware. A detailed explanation of the Hardware used can be found here.
The coding used for this project is a combination of Verilog and C since FPGA and the 6502 are used. The Verilog Coding is used to extract Nintendo Sound Format files (.nsf) from the SD card reader onto the FPGA. The NSF files can be loaded on to the FPGA through the 6502 processor which has been coded in the C language using standard functions. NSF files can be stored on the SD card using a computer.
The NIOS II FPGA acts as an NSF player in this particular project. It can be used to control playback, stop tracks or forward and rewind to the next or previous track.
Using just 4 channels in the APU the developers have done an amazing job and an example of the fruits of their labour (and an inspiration!) can be seen here.
By A. Heil and S. Zhao
July 7th, 2016
Hello explorers of the FPGA Kingdom! Today’s project digs into the scope of FPGA as a tool that can replace conventional techniques further. VGA or video processing through conventional means requires a frame buffer which stores a block of data regarding pixel information in the system RAM for video display which is transferred to the display device at the right time using real time means. FPGAs can replace these frame buffers in a novel way such that the system RAM utilized for this remains free at the cost of a little more real time computation.
The developers used a DE2-115 FPGA board along with a Wolfson Audio Codec to animate 4 characters on the screen such that they appear to be dancing to the beats of the music played. Apart from those hardware elements, a monitor (graphics module) was used.
The coding was done by the developers using MATLAB since the project requires the use of filters through DFT and MATLAB has functions readily available for this. THE DFT is used to filter out the lowest frequency component (which will be the percussions or beats) and then calculate the interval at which this repeats. Once this information is obtained, the music is passed on from the ADC of the Codec to the monitor through the FPGA for animation.
The graphics on screen are programmed in modules such as a “head” file, a “body” file, an “arms” file, and a “legs” file which induce movements to the body parts depending upon the information processed by the FPGA from the rhythm of the music played. For a detailed explanation regarding the project, design, testing and systems integration you can visit the developers’ page here.
The result of this project can be seen here.
Though the project is not a replacement to the fast and efficient way of processing VGA through Frame buffers, it certainly explores the academic value and versatility of the FPGA as a tool that can be used for multiple purposes.
By C. Archard and N. Levy
June 30th, 2016
Greetings FPGA lovers! Today’s post is about building your own mini computer using FPGA. The project has been inspired by the first SSEM, popularly called the Manchester baby. The project resembles its inspiration in certain aspects, but being a homemade CPU with minimal components and coding, the specs are not as formidable as the SSEM.
The author has used a standard FPGA Papilo one 500k board, an 8×8 LED strip and a set of switches. The system has been designed for a total RAM of 64 bits, and the LED strip shows the RAM configuration every time data is entered at a new address. Besides this, the author has also used a rechargeable battery, charging circuit, clipper circuit to avoid excess voltage and a number of peripheral ICs.
The coding followed for FPGA is based on simple VHDL (.vhd) and being an open source project, the author has shared all VHDL code here. The CPU is programmed directly using the address and data switches. A number of values can be stored just by setting the CPU on the User mode and entering data to the addresses of the 64 bit RAM.
The system also has an adjustable clock which helps while simulating and running the code in variable clock speeds. The author has successfully demonstrated through the video that the CPU can work as a Random number Generator (from 1 to 6) and a pendulum. Besides this the CPU can also be connected to external components like an array of LEDs for clarity of output.
Though the FPGA based C88 Homebrew CPU has limited RAM and storage capabilities, it is still a great start to create experimental modules and platforms using FPGA that can host a number of applications.
By Daniel Bailey
June 28th, 2016
Hello FPGA enthusiasts! Today’s project takes sound production using FPGA to another level. The project under focus is building an electric keyboard/composer using FPGA. The keyboard acts as a song tune composer where a network of switches on the FPGA board is connected in precedence such that while a switch is on, the corresponding note plays.
The major hardware components needed are just a FPGA board (you may need to adapt this project to your own board), a speaker capable of playing a wide range of frequencies, and not just a monotone, and an auxiliary cable or suitable wires for connecting the speaker to the FPGA board.
The coding has been done using Xilinx ISE in the VHDL (.vhd). The author has given a detailed pin assignment as well as a basic VHDL background explanation. The code has been shared from step 5 to 9 and each module has been well explained by the author. The modules basically consist of a frequency division for playing different frequencies of sound and process statements for fixing parameters like precedence and sensitivity.
Setting the port map and executing the program has been explained in steps 10 and 11. By switching different switches you get different tones, though combinational tones cannot be made since precedence is followed.
The show must go on!
June 23rd, 2016
Hello FPGA lovers! Today we are going to share another instalment of our YM 2151 post series.
According to the author of the original article (in Spanish), the best way to produce sound using the YM 2151 is to use the 6809 assembler which is a cross targeting assembler seen usually in Motorola and Hitachi Devices. The author has made use of a MAME or a Multiple Arcade Machine Emulator which is the best platform for recreating arcade hardware since conventional FPGA Tools are unavailable for this project (in Spanish).
The author has simulated a project in MAME and has shared the code and registry values along with its explanation. This is more than a blessing in disguise since there is very little documentation regarding the actual simulation and synthesis of sound with the YM 2151 available on the Internet.
The Registry values, name and a short description regarding the function of each register is given in a comprehensive table by the author. The most important of these registry value combinations are:
- Registry $60- $7F with Value $ 00 for volume.
- Registry $20 with value $C for Left Right output control.
- Registry $48 with value $4A for the notes and transposing it through octaves of 8 notes
Though there are a number of other registers given by the author of equal significance, the most important of these is the above quoted three registers as they play a pivotal role in sound production.
The author has also shared the asm 6809 assembler code. The table of registers executed in the code (in Spanish) can however produce a sound just once. To repeat these sounds and modulate frequencies to get a set of notes to play actual music might seem a bit tedious as there will be a need for repeated execution of the source code with some variations in registry values to produce different sounds.
June 21st, 2016
Hi there FPGA lovers! Here we have another release of our series of YM2151 posts.
To recreate the YM 2151 in FPGA using VHDL, every aspect of the YM 2151 needs to be mapped on to the recreation platform. However an interesting aspect regarding the YM 2151 is that it uses random values for generation of noise (in Spanish) sound outputs like shocks, explosions and other disruptive sounds. While a general range of the signals used to generate this noise can be sampled, the YM 2151 has close to 18 bits for random signal generation which leads to a total of 218 signals.
The YM 2151 however uses a Linear Feedback Shift Register for this random sequence generation, and this considerably narrows down the possibility from more than a hundred thousand samples to a very narrow range. The output noise sequence can be predicted because of the feedback element, as every feedback signal can only have one selected output.
The MAME Source code for the emulator consists of a code for generating noise. This code has been used by the author to share a set of 256 samples. Though the samples appear to be seemingly random at first, a definitive pattern can be decoded from the samples depending upon the feedback given.
The Berlekamp- Massey Algorithm was used by the author to conclude that a definite relationship exists between the feedback and generated sequence for all bits except 0 and 4, contrary to the assumed 0 and 8 in the beginning. However the fact that the outputs after 0 and 4 cannot be predicted leads to the fact that there might be more than 218 samples. Thus from a set of more than hundred thousand random signals to generate noise in the YM 2151, the author has narrowed down the possibility to a handful of feedback signals which can be used to create the clone of YM 2151 in Verilog for FPGA.
June 16th, 2016
Hi FPGA lovers! In our conquest to find studio quality sound, we stumbled upon the YM 2151 FM Synth Chip which has been used by Yamaha from time immemorial in a number of their electronic keyboards and arcade games. The YM 2151 has a Digital output rather than an analog output and this makes it ideal for further signal processing using DSP. However due to the absence of an on chip DAC, the YM 2151 needs a suitable DAC chip that does not add substantial noise while analog reconstruction.
Today’s post is a detailed study of the YM 2151 and its coupling with YM 3012 DAC which are almost like inseparable siblings of the Yamaha family. The YM 2151 is a 24 pin IC which gives a 16 bit output. The first 3 bits have no significant value, whereas the next 10 bits in order are the significant bits or mantissa and the last 3 bits are the exponents. The author has conducted a number of measures for a fixed value of supply voltage and has shared the results in his post.
The 3 parameters of concern are “d”, “n” and “m” which are the value of mantissa, exponent value and size of LSB respectively. The output voltage of the chip is given by a fixed relationship between these parameters where Vout= m*d + n.
From this result, the Verilog code for YM 3012 in the post starts making sense. The code has been designed around the fact that the base voltage is Vdd/2. However no explanation was given as to why this particular voltage was chosen. From this result, we deduce that Vdd/2 is the principle value because it supports maximum swing in positive and negative directions. This way the 10 bit resolution of the mantissa can be put to full use to produce the desired harmonic frequencies of high quality and clarity.
This is the reason why the YM 3012 DAC is best for this Synth chip, because it is essentially the second half of Yamaha’s FM Synth Chip design. The chip has been broken into two parts (the 2151 and 3012) to give the benefit of getting a 16 bit Digital output for further processing before reconstruction of the analog signal.
This makes the YM 2151 perfect for creating sound boards. The YM 2151 can be used in combination with a FPGA to recreate any themes. The FPGA adds a degree of flexibility in the chip’s output since the output of the YM 2151 is digital and can be easily processed by the FPGA.