Papilio One Overview

The Papilio is a FPGA development board based on the Xilinx Spartan 3E FPGA (datasheet). It has 48 I/O lines, dual channel USB, integrated JTAG programmer, 4 power supplies, and a power connector. It provides everything needed to start learning Digital Electronics?.

Quick Links

Xilinx Spartan-3E datasheet

Spartan-3E User's guide

Xilinx UFC file

Pin mapping


EAGLE files (License CC-BY-SA-NC)



  • Four independent power rails at 5V, 3.3V, 2.5V, and 1.2V.
  • Power supplied by a power connector or USB.
  • DC Input Jack.
    • Input Voltage (recommended): 6.5-15V


  • Two channel USB connection for JTAG and serial communications implemented with FT2232D.
  • EEPROM memory to store configuration settings for FT2232 USB chip.

Spartan 3E FPGA

  • 32 MHz oscillator that can be used by the Digital Clock Manager to provide self calibrating, fully digital solution for distributing, delaying, multiplying, dividing, and phase-shifting clock signals.
  • VTQFP-100 footprint that supports Xilinx XC3S100E, XC3S250E, and XC3S500E parts.
  • I/O blocks to control data flow between the I/O and the internal logic. It supports bidirectionnal and 3-state operation. The I/O are configurable on the board for 1.2V, 2.5V or 3.3V support.

SPI Flash


  • 48 bidirectional I/O lines which can be split up as:
    • 1x 32 Bit Wing or
    • 3x 16 Bit Wings or
    • 6x 8 Bit Wings
  • .1" spacing for compatibility with bread boards.


I/O Blocks

The I/O blocks provides programmable interface between pins and the Spartan-3E internal logic.

  • Features:
    • Programmable pull-down, pull-up and float resistors (Pull-down by default on unused pins).
    • Programmable input delay.
    • Optionnal keeper circuit (keeps last logic level, see spartan-3E datasheet page 18).
    • 2 to 16 mA programmable output current drive strength.
    • All I/O pins are in high-impedance state during configuration (program loading). Unused pins are pull-down inputs by default with the Xilinx ISE software.

I/O Banks

  • The VCCO jumper selects the voltage for all of the I/O lines, the options are 1.2V, 2.5V, and 3.3V. The recommended setting is 3.3V since most peripherals operate at 3.3V.


The Papilio One can be powered from the USB connector, an external power supply, or a battery. The PWRSELECT jumper controls whether the USB connector or the Power Jack/PWRIN connectors are active.

Power Selection

When the USB connector is selected up to 500mA of current is supplied to the 1.2V, 2.5V, and 3.3V LD1117 voltage regulators. The 5V power rail is supplied directly by the USB port and the 5V LD1117 power regulator is inactive.

When the power jack or battery is selected the 5V LD1117 voltage regulator supplies up to 800mA of current to the 1.2V, 2.5V, and 3.3V LD1117 voltage regulators. The power jack or battery must provide at least 6V in order to generate the desired 5V output.


The JTAG programming pins on the Spartan 3E always operate at 2.5V while the connected JTAG pins of the FT2232D always operate at 3.3V. This difference in voltage can cause the Spartan 3E to send reverse current back on the 2.5V power rail. The RPAR resistor provides a shunt for this reverse current to be dissipated. The Xilinx application notes recommend the use of RPAR in the case that a voltage regulator cannot handle reverse current. The LD1117 datasheet does not indicate that it can handle reverse current so RPAR was included. Testing has shown that the LD1117 seems to handle the reverse current just fine but boards will be populated with RPAR as a safety precaution. The RPAR resistor consumes 25mA of current so if a battery is being used it is recommended to remove the RPAR resistor to help extend battery life. Please understand that the possible effects of removing the RPAR resistor are the 2.5V rail going higher than 2.5V and possibly damaging the 2.5V voltage regulator. There is an interesting discussion about the need for RPAR here.

Power Jack

  • Input: 6-15V DC
  • Current: Draws up to 800mA
  • Size: 2.1mm
  • Polarity: Positive Tip


The on-board SPI Flash provides 4Mbits of space to store a bitstream that is loaded by the FPGA at start-up. Bitstreams are loaded to SPI Flash using the Papilio Loader?.


The Papilio One uses a FTDI 2232D USB chip which provides two channels over one USB connection. One of the channels is configured as a simple UART device and shows up as a virtual COM port. The other channel takes advantage of the MPSSE (Multi-Protocol Synchronous Serial Engine) functionality to implement a high speed JTAG channel for programming the Xilinx Spartan 3E.


The first time the Papilio One is plugged into the computer it will be necessary to install the FTDI device drivers. Drivers can be downloaded from the FTDI website.


When the Papilio One is plugged into the USB port both channels will be detected and will show up under the Control Panel as a virtual COM port. The second virtual COM port is the UART channel.


The Xilinx device is programmed using any application that can support the FT2232D MPSSE JTAG mode. The Papilio Loader is one such application.

JTAG Programming Port

The JTAG programming port is included for use with external JTAG programmers such as the Xilinx JTAG cables. The Xilinx tools such as Impact and the EDK do not support FT2232D based programmers nor does Xilinx provide any method to add support for non-Xilinx programmers. This external port is provided as a means to use the Xilinx tools with the Papilio One. The Xilinx tools can still be used without an Xilinx programmer by generating bitstreams that can be loaded by the Papilio Loader.

TEMPORARY LIMITATION: In order to use the external JTAG port the FT2232D lines that are connected to the JTAG port need to be put into a HIGH-Z state. This has not been tested yet and will probably require a special application.


Custom VID/PID and configuration data can be loaded into the provided EEPROM using the FTDI MProg application.



The Papilio One has a 32Mhz oscillator that can be converted to any speed desired inside the FPGA using a Digital Clock Manager. The Spartan 3E provides 4 Digital Clock Managers.


The Papilio One has a power LED, a RX LED, and a TX LED. The power led lights up to indicate that power is being supplied to the board while the RX and TX led's show UART traffic.

Aditionnal information:



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