The address bus (output of the Z80) and the data bus (inout of the Z80) are shared with all components.
What we need is some logic to turn the read/write/input/output Z80 commands into read/xrite commands for each of the modules.
This takes, as input:
- the RD,WR,IO signals,
- the adress bus (higher bits to route the memory accesses, bits 0,6,7 to route the IO accesses)
This outputs RD,WR signals for each component: RAM, ROM, VDP, PSG, IO