The "Sump" Logic Analyzer supports 32 channels with 6K sample memory or 8 channels with 24K and runs up to 200MHz. The included Java client application allows waveform exploration as well as SPI and I2C protocol analysis. This project is synthesized for the Papilio One and shares the same code base as the Openbench Logic Sniffer project.
NOTE: The current 2.12 release is based on the Openbench Logic Sniffer 2.12 source code. There are issues with RLE, test mode, and there are some failing timing constraints in the project. This release has not been well tested, it is being released while the new Verilog branch of the project is completed. The Verilog branch should fix all of the above issues and will be available soon.
1.2V, 2.5V, and 3.3V signals can be sampled directly on Wing Slot A and C. Using a Input Buffer Wing allows 5V signals (up to 7V) to be sampled on either Wing
|Optional Wings||Wing Slot|
|Input Buffer Wing||A|
|Input Buffer Wing||B|
|Ready to run bitstream for the Papilio One 500K board. Version 2.12, use Papilio Loader to load the bitstream.||Sump_Logic_Analyzer_P1_500K.bit|
|Ready to run bitstream for the Papilio One 500K board. Version 2.12, use Papilio Loader to load the bitstream.||Sump_Logic_Analyzer_P1_250K.bit|
|Source code version 2.12. Use Xilinx ISE Webpack to open project.||Papilio_One_Sump_LA_VHDL_source_2.12.zip|
|Java Client - Download the latest client from Jawi's Alternate Client Homepage.||Jawi Client 0.9.2|
|Quick Start package, download this to get started without any fuss. A loader script and Jawi's client make this ready to go.||Papilio_One_Logic_Analyzer_QuickStart_2.12.zip|
2/4/2011 - Version 2.12 Released
Version 2.12 is based on the OpenBench Logic Sniffer branch of the "Sump" Logic Analyzer. The following new features are included: