Papilio.PapilioPro History

Hide minor edits - Show changes to output

June 16, 2015, at 11:45 AM by Jack Gassett -
Changed line 41 from:
*64Mbit Macronix MX25L6445 SPI Flash %newwin%([[http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/3F21BAC2E121E17848257639003A3146/$File/MX25L6445E,%203V,%2064Mb,%20v1.8.pdf|Datasheet]])
to:
*64Mbit Macronix MX25L6445 SPI Flash %newwin%([[http://www.macronix.com/Lists/Datasheet/Attachments/2474/MX25L6445E,%203V,%2064Mb,%20v1.8.pdf|Datasheet]])
Changed line 135 from:
The 64Mbit Macronix %newwin%[[http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/3F21BAC2E121E17848257639003A3146/$File/MX25L6445E,%203V,%2064Mb,%20v1.8.pdf|MX25L6445]] SPI Flash chip is the largest ever included with a Papilio FPGA. It is the largest available in the 8-SOIC footprint, and is included for good reason! The new multi-boot feature of the Spartan 6 means we can put as many FPGA bit files on the SPI Flash as will fit and use a "golden image" to select which one will boot at startup. Spartan 6 LX9 bit files are 333KBytes in size which means that the Papilio Pro can save up to 23 bit files in SPI Flash. Or, we can save and retrieve user data using techniques like the SmallFS filesystem or [[http://www.papilio.cc/index.php?n=Playground.Bootstrap|bootstrap code]] that loads data from SPI Flash to SRAM at startup.
to:
The 64Mbit Macronix %newwin%[[http://www.macronix.com/Lists/Datasheet/Attachments/2474/MX25L6445E,%203V,%2064Mb,%20v1.8.pdf|MX25L6445]] SPI Flash chip is the largest ever included with a Papilio FPGA. It is the largest available in the 8-SOIC footprint, and is included for good reason! The new multi-boot feature of the Spartan 6 means we can put as many FPGA bit files on the SPI Flash as will fit and use a "golden image" to select which one will boot at startup. Spartan 6 LX9 bit files are 333KBytes in size which means that the Papilio Pro can save up to 23 bit files in SPI Flash. Or, we can save and retrieve user data using techniques like the SmallFS filesystem or [[http://www.papilio.cc/index.php?n=Playground.Bootstrap|bootstrap code]] that loads data from SPI Flash to SRAM at startup.
August 13, 2014, at 11:39 AM by Jack Gassett -
Changed line 38 from:
*High efficiency LTC3419 Step Down Dual Voltage Regulator %newwin%([[http://cds.linear.com/docs/Datasheet/3419fa.pdf|Datasheet]])
to:
*High efficiency LTC3419 Step Down Dual Voltage Regulator %newwin%([[http://cds.linear.com/docs/en/datasheet/3419fa.pdf|Datasheet]])
May 08, 2013, at 11:00 PM by Jack Gassett -
Added lines 164-168:
|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio Pro Pin||
||CLK||Input||External 32Mhz Oscillator||N/A||N/A||P94||
\\
Added lines 184-191:
|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio Pro Pin||
||JTAG_TMS||Input||JTAG TMS||N/A||N/A||P107||
||JTAG_TCK||Input||JTAG TCK||N/A||N/A||P109||
||JTAG_SI||Input||JTAG SI||N/A||N/A||P64||
||JTAG_SO||Output||JTAG SO||N/A||N/A||P65||
\\
Changed lines 199-204 from:
to:
|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio Pro Pin||
||RESET||Input||FPGA Reset||N/A||N/A||P37||
\\
Added lines 212-216:
|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio Pro Pin||
||LED1||Output||USER LED1||N/A||N/A||P112||
\\
May 08, 2013, at 10:54 PM by Jack Gassett -
Changed line 105 from:
||Name||Direction||Function||Arduino Pin||Papilio Wing Pin||Papilio Pro Pin||
to:
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio Pro Pin||
Changed lines 108-109 from:
to:
\\
Added lines 137-144:

|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio Pro Pin||
||FLASH_CS||Output||SPI Flash Chip Select||N/A||N/A||P38||
||FLASH_CLK||Output||SPI Flash Clock||N/A||N/A||P70||
||FLASH_MOSI||Output||SPI Flash Master Out Slave In (MOSI)||N/A||N/A||P64||
||FLASH_MISO||Input||SPI Flash Master In Slave Out (MISO)||N/A||N/A||P65||
\\
May 08, 2013, at 10:48 PM by Jack Gassett -
Added lines 102-108:


|| class=prettytable2
||Name||Direction||Function||Arduino Pin||Papilio Wing Pin||Papilio Pro Pin||
||RX||Input||FPGA Serial Receive (MISO)||N/A||N/A||P101||
||TX||Output||FPGA Serial Transmit (MOSI)||N/A||N/A||P105||
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||class=prettytable2
to:
||class=prettytable3
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(:table border='0' cellpadding='5' cellspacing='1' width='100%' class=prettytable2:)
(:head :)Papilio Board
(:head :)18Kbit BRAM Blocks
(:head :)Max SRAM
(:head :
)Usable SRAM
(:cellnr :)Papilio Pro
(:cell :
)32
(:cell :)576Kbit (72KByte)
(:cell :)512Kbit (64KByte)
(:cellnr :)Papilio One 500K
(:cell :)20
(:cell :)360Kbit (45KByte)
(:cell :)320Kbit (40KByte)
(:cellnr :)Papilio One 250K
(:cell :)12
(:cell :)216Kbit (27KByte)
(:cell :)192Kbit (24KByte)
(:tableend:)
to:
||class=prettytable2
||Papilio Board||18Kbit BRAM Blocks||Max SRAM||Usable SRAM||
||Papilio Pro||32||576Kbit
(72KByte)||512Kbit (64KByte)||
||Papilio One 500K||20||360Kbit (45KByte
)||320Kbit (40KByte)||
||
Papilio One 250K||12||216Kbit (27KByte)||192Kbit (24KByte)
\\
Changed lines 67-83 from:
(:table border='0' cellpadding='5' cellspacing='1' width='100%':)
(:head bgcolor=#429ae0 :)Papilio Board
(:head bgcolor=#429ae0 :)18Kbit BRAM Blocks
(:head bgcolor=#429ae0 :)Max SRAM
(:head bgcolor=#429ae0 :)Usable SRAM
(:cellnr bgcolor=#c5d7dd:)Papilio Pro
(:cell bgcolor=#c5d7dd:)32
(:cell bgcolor=#c5d7dd:)576Kbit (72KByte)
(:cell bgcolor=#c5d7dd:)512Kbit (64KByte)
(:cellnr bgcolor=#7fc5e4:)Papilio One 500K
(:cell bgcolor=#7fc5e4:)20
(:cell bgcolor=#7fc5e4:)360Kbit (45KByte)
(:cell bgcolor=#7fc5e4:)320Kbit (40KByte)
(:cellnr bgcolor=#c5d7dd:)Papilio One 250K
(:cell bgcolor=#c5d7dd:)12
(:cell bgcolor=#c5d7dd:)216Kbit (27KByte)
(:cell bgcolor=#c5d7dd:)192Kbit (24KByte)
to:
(:table border='0' cellpadding='5' cellspacing='1' width='100%' class=prettytable2:)
(:head :)Papilio Board
(:head :)18Kbit BRAM Blocks
(:head :)Max SRAM
(:head :)Usable SRAM
(:cellnr :)Papilio Pro
(:cell :)32
(:cell :)576Kbit (72KByte)
(:cell :)512Kbit (64KByte)
(:cellnr :)Papilio One 500K
(:cell :)20
(:cell :)360Kbit (45KByte)
(:cell :)320Kbit (40KByte)
(:cellnr :)Papilio One 250K
(:cell :)12
(:cell :)216Kbit (27KByte)
(:cell :)192Kbit (24KByte)
Changed line 119 from:
The Papilio Pro includes a 64Mbit Micron %newwin%[[http://download.micron.com/pdf/datasheets/dram/sdram/64MSDRAM.pdf|MT48LC4M16]] SDRAM chip. This additional SDRAM will open up a whole new breed of FPGA applications for the Papilio. The timing requirements and refresh signals of the SDRAM chip do make interfacing it more of a challenge then interfacing regular SRAM, or the internal BRAM. We are working on a SDRAM controller that you can drop into your designs so the SDRAM can be used like regular SRAM.
to:
The Papilio Pro includes a 64Mbit Micron %newwin%[[http://download.micron.com/pdf/datasheets/dram/sdram/64MSDRAM.pdf|MT48LC4M16]] SDRAM chip. This additional SDRAM will open up a whole new breed of FPGA applications for the Papilio. The timing requirements and refresh signals of the SDRAM chip do make interfacing it more of a challenge than interfacing regular SRAM, or the internal BRAM. We are working on a SDRAM controller that you can drop into your designs so the SDRAM can be used like regular SRAM.
Changed line 194 from:
(:include PapilioProLinks :)
to:
(:include Papilio.PapilioProLinks :)
Changed line 194 from:
(:includefieldpage field=Main Main.PapilioProPapilioProLinks :)
to:
(:include PapilioProLinks :)
Changed line 194 from:
(:includefieldpage field=Papilio Papilio.PapilioProPapilioProLinks :)
to:
(:includefieldpage field=Main Main.PapilioProPapilioProLinks :)
Changed line 194 from:
(:include PapilioProLinks :)
to:
(:includefieldpage field=Papilio Papilio.PapilioProPapilioProLinks :)
Changed lines 194-202 from:
'''Papilio Pro Design Files'''
->[[http
://forum.gadgetfactory.net/index.php?/files/getdownload/34-papilio-pro-generic-ucf/|Papilio Pro Generic User Constraint File (UCF)]]
->[[https://github.com/GadgetFactory/Papilio-Pro/archive/master.zip|Papilio Pro EAGLE Design Files]]
->[[https://github.com/GadgetFactory/Papilio-Pro/blob/master/BPC3010_Papilio_Pro.pdf?raw=true|Papilio Pro Schematic (PDF)]]

'''Community Links'''
->[[http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/papilio-pro/|Papilio Pro Project Showcase]]
->[[http://forum.gadgetfactory.net/index.php?/forum/102-papilio-pro-and-papilio-plus/|Papilio Pro Forum]]
->[[http://forum.gadgetfactory.net/index.php?/tags/downloads/papilio+pro/|Papilio Pro Downloads]]
to:
(:include PapilioProLinks :)
Changed line 157 from:
The Papilio Pro has a 32Mhz oscillator that can be converted to any speed desired inside the FPGA using the Clock Management Tile (CMT). There are two PLLs and two [[http://www.papilio.cc/index.php?n=Papilio.DigitalClockManager|Digital Clock Manamgers (DCM)]] available for your designs.
to:
The Papilio Pro has a 32Mhz oscillator that can be converted to any speed desired inside the FPGA using the Clock Management Tile (CMT). There are two PLLs and two [[http://www.papilio.cc/index.php?n=Papilio.DigitalClockManager|Digital Clock Managers (DCM)]] available for your designs.
Deleted line 202:
Deleted line 203:
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\\
Added lines 1-242:
(:notabledit:)
(:include HardwareHeader:)

>>lrindent round frame float:right width:400px<<
'''Contents'''
[[<<]]
[[#Overview|Overview]][[<<]]
[[#PProFPGA|Spartan 6 LX9 FPGA]][[<<]]
[[#PProPower|Power]][[<<]]
[[#PProUSB|Dual Channel USB]][[<<]]
[[#PProSdram|SDRAM]][[<<]]
[[#PProSPIFlash|SPI Flash]][[<<]]
[[#PProIO|I/O]][[<<]]
[[#PProOscillator|Oscillator]][[<<]]
[[#PProJTAG|JTAG]][[<<]]
[[#PProReset|Reset]][[<<]]
[[#PProUserLED|User LED]][[<<]]
[[#PProLinks|Links]][[<<]]
[[#PProLicense|License]][[<<]]
[[#Images|Images]][[<<]]
>><<

[[#Overview]]
!!Papilio Pro
>>round frame<<
The Papilio Pro is an Open Source FPGA development board based on the
Xilinx Spartan 6 LX FPGA.
It has 48 I/O lines, dual channel USB, integrated JTAG
programmer, 64Mb SDRAM, and an efficient switching power supply.
>><<

>>round frame float:left width:400px bgcolor=#ffffff<<
%width=500%[[Attach:ppro.jpg|Attach:ppro.jpg]]
>><<
[[<<]]

*Spartan 6 LX9 FPGA %newwin%([[http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf|Datasheet]])
*High efficiency LTC3419 Step Down Dual Voltage Regulator %newwin%([[http://cds.linear.com/docs/Datasheet/3419fa.pdf|Datasheet]])
*Dual Channel FTDI FT2232 USB 2.0 Full Speed Interface %newwin%([[http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232D.pdf|Datasheet]])
*64Mbit Micron MT48LC4M16 SDRAM %newwin%([[http://download.micron.com/pdf/datasheets/dram/sdram/64MSDRAM.pdf|Datasheet]])
*64Mbit Macronix MX25L6445 SPI Flash %newwin%([[http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/3F21BAC2E121E17848257639003A3146/$File/MX25L6445E,%203V,%2064Mb,%20v1.8.pdf|Datasheet]])
*48 I/O pins arranged in a Papilio Wing form factor
*32Mhz Crystal Oscillator
[[<<]]
----
[[#PProFPGA]]
!!!Spartan 6 LX9 FPGA
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:fpga_callout.png
The Papilio Pro's %newwin%[[http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf|Spartan 6 FPGA]] offers some exciting new features over the Spartan 3:

'''Digital Signal Processing (DSP) Slices'''
->18 DSP48A1 Slices for DSP functions.
'''Clock Management Tile (CMT)'''
->The Papilio One (Spartan 3E) offered 4 Digital Clock Managers (DCM) but did not offer any Phase-Locked Loops (PLL). The Papilio Pro (Spartan 6) offers the more flexible CMT which provides both DCM's and PLL's!
%rframe text-align=center width=200px% [[Attach:fpga_schematic.png|Attach:fpga_schematic.png]]|'''FPGA Schematic'''
\\
\\

'''New I/O Standards'''
->The Papilio Pro (Spartan 6) has direct TMDS I/O support which means that DVI and HDMI interfaces can be implemented without any extra chips.
'''Multi-Boot Support'''
->You can load multiple bit files into the SPI Flash and setup the first bit file to select which one will be loaded. With some work we could make a ZPUino based bootloader that would have a VGA interface to choose which bit file to load.
'''BRAM Memory Blocks'''
->The Spartan 6 allows 18Kbit BRAM blocks to be split into two 9Kbit BRAM blocks.
->There is more built in SRAM - there is 64KByte of internal SRAM which is just enough to recreate the Commodore 64!

(:table border='0' cellpadding='5' cellspacing='1' width='100%':)
(:head bgcolor=#429ae0 :)Papilio Board
(:head bgcolor=#429ae0 :)18Kbit BRAM Blocks
(:head bgcolor=#429ae0 :)Max SRAM
(:head bgcolor=#429ae0 :)Usable SRAM
(:cellnr bgcolor=#c5d7dd:)Papilio Pro
(:cell bgcolor=#c5d7dd:)32
(:cell bgcolor=#c5d7dd:)576Kbit (72KByte)
(:cell bgcolor=#c5d7dd:)512Kbit (64KByte)
(:cellnr bgcolor=#7fc5e4:)Papilio One 500K
(:cell bgcolor=#7fc5e4:)20
(:cell bgcolor=#7fc5e4:)360Kbit (45KByte)
(:cell bgcolor=#7fc5e4:)320Kbit (40KByte)
(:cellnr bgcolor=#c5d7dd:)Papilio One 250K
(:cell bgcolor=#c5d7dd:)12
(:cell bgcolor=#c5d7dd:)216Kbit (27KByte)
(:cell bgcolor=#c5d7dd:)192Kbit (24KByte)
(:tableend:)

>>important<<
BRAM's are 18Kbit in size including two parity bits. In most cases the two parity bits are not used so the BRAM's usable size becomes 16Kbit. If your design can use an 18 bit wide bus then it is possible to utilize the parity bits for data and gain access to all 18Kbit memory space.
>><<
[[<<]]
----
[[#PProPower]]
!!!Power
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:power-callout.png
%rframe text-align=center height=220px% [[Attach:power-schematic.png|Attach:power-schematic.png]]|'''Power Schematic'''

One of the big improvements with the Papilio Pro is its power supply. The Spartan 6 simplifies the power requirements which allowed us to use a high efficiency %newwin%[[http://cds.linear.com/docs/Datasheet/3419fa.pdf|LTC3419]] switching power supply at about the same component cost as the Papilio One's power supply. The linear regulators used in the Papilio One would noticeably heat up when a complicated, high speed design, like the ZPUino, was running. With the Papilio Pro there is no detectable heat generated, even when the most demanding designs are running!
[[<<]]
----
[[#PProUSB]]
!!!Dual Channel USB
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:usb-callout.png
The Papilio Pro uses the same %newwin%[[http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232D.pdf|FT2232]] dual channel USB chip that the Papilio One does.

*Channel A is connected to the Papilio Pro in an Asynchronous serial UART configuration that is capable of speeds up to 2MHz.
*Channel B is connected to the JTAG pins of the Papilio Pro and provides very fast programming of the FPGA (500mS).
[[<<]]

>>tip<<
The Papilio Pro includes a reset header (JP4) that can be populated with a jumper to hold the Spartan 6 FPGA in permanent reset mode. This frees up the JTAG Header to be used as an FT2232 JTAG/SPI/MPSSE Programmer.
>><<

%cframe text-align=center width=500% [[Attach:usb-schematic.png|Attach:usb-schematic.png]]|'''USB Schematic'''
[[<<]]
----
[[#PProSdram]]
!!!SDRAM
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:sdram-callout.png
%rframe height=300px% [[Attach:sdram-schematic.png|Attach:sdram-schematic.png]]
The Papilio Pro includes a 64Mbit Micron %newwin%[[http://download.micron.com/pdf/datasheets/dram/sdram/64MSDRAM.pdf|MT48LC4M16]] SDRAM chip. This additional SDRAM will open up a whole new breed of FPGA applications for the Papilio. The timing requirements and refresh signals of the SDRAM chip do make interfacing it more of a challenge then interfacing regular SRAM, or the internal BRAM. We are working on a SDRAM controller that you can drop into your designs so the SDRAM can be used like regular SRAM.

\\

!!!SDRAM Designs
*[[http://hamsterworks.co.nz/mediawiki/index.php/SDRAM_Memory_Controller|Hamster's SDRAM Controller]]
*[[https://github.com/alvieboy/ZPUino-HDL/blob/dcache/zpu/hdl/zpuino/boards/papilio-pro/S6LX9/sdram_hamster.vhd|Alvie's ZPUino SDRAM controller.]] (derived from Hamster's SDRAM controller).
*[[https://github.com/alvieboy/ZPUino-HDL/blob/dcache/zpu/hdl/zpuino/boards/papilio-pro/S6LX9/sdram_wrap.vhd|Wishbone wrapper for Alvie's SDRAM controller.]]
*[[http://www.xilinx.com/support/documentation/application_notes/xapp394.pdf|XAPP 394 Interfacing Mobile SDRAM with CPLD's.]]
[[<<]]

>>tip<<
The ZPUino Soft Processor includes a SDRAM controller which gives your ZPUino sketches 8MByte of code space!
>><<
[[<<]]
----
[[#PProSPIFlash]]
!!!SPI Flash
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:flash-callout.png
%rframe width=300px% [[Attach:flash-schematic.png|Attach:flash-schematic.png]]
The 64Mbit Macronix %newwin%[[http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/3F21BAC2E121E17848257639003A3146/$File/MX25L6445E,%203V,%2064Mb,%20v1.8.pdf|MX25L6445]] SPI Flash chip is the largest ever included with a Papilio FPGA. It is the largest available in the 8-SOIC footprint, and is included for good reason! The new multi-boot feature of the Spartan 6 means we can put as many FPGA bit files on the SPI Flash as will fit and use a "golden image" to select which one will boot at startup. Spartan 6 LX9 bit files are 333KBytes in size which means that the Papilio Pro can save up to 23 bit files in SPI Flash. Or, we can save and retrieve user data using techniques like the SmallFS filesystem or [[http://www.papilio.cc/index.php?n=Playground.Bootstrap|bootstrap code]] that loads data from SPI Flash to SRAM at startup.
[[<<]]

----
[[#PProIO]]
!!!I/O
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:io-callout.png
%rframe height=250px% [[Attach:io-schematic.png|Attach:io-schematic.png]]
The I/O of the Papilio Pro is backwards compatible with the Papilio One, all existing Papilio Wings and MegaWings work with the Papilio Pro.

The major difference between the Papilio Pro and Papilio One with respect to User I/O is the available voltage levels. The Papilio Pro sets all I/O voltage pins to 3.3V while the Papilio One can switch between 1.2V, 2.5V, and 3.3V. This was a seldom used feature that was dropped in the Papilio Pro for greater compatibility. Additionally, the Papilio Pro does not provide a 2.5V power rail, the 2.5V pin on the Wing Header is left unconnected. There are no Wings or MegaWings that use 2.5V power and there probably never will be... 3.3V seems to be the defacto standard for current peripherals.
[[<<]]

----
[[#PProOscillator]]
!!!Oscillator
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:osc-callout.png
%rframe width=300px% [[Attach:osc-schematic.png|Attach:osc-schematic.png]]
The Papilio Pro has a 32Mhz oscillator that can be converted to any speed desired inside the FPGA using the Clock Management Tile (CMT). There are two PLLs and two [[http://www.papilio.cc/index.php?n=Papilio.DigitalClockManager|Digital Clock Manamgers (DCM)]] available for your designs.
[[<<]]

----
[[#PProJTAG]]
!!!JTAG
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:jtag-callout.png
%rframe width=200px% [[Attach:jtag-schematic.png|Attach:jtag-schematic.png]]
The JTAG header on the Papilio Pro is provided for a couple different reasons:

'''Use a Xilinx Programming Cable'''
->If you want to use the Xilinx tools such as EDK, Chipscope, or Impact with the Papilio you need a way to use a Xilinx programming cable. The Papilio has a Xilinx JTAG header but the problem is that in the default mode the FT2232D USB chip is connected to the JTAG pins and interferes with programming. What is needed is to put the FT2232 into a mode where the JTAG pins go into High-Z leaving the Xilinx JTAG pins free for the programming cable. To learn more about using a Xilinx Programming Cable visit the [[http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/xilinx-programming-cable-with-papilio-r39|original forum post]] or [[http://www.gadgetfactory.net/2012/09/use-a-xilinx-programming-cable-with-the-papilio/|blog post]].

'''Bypass the FPGA and use the FT2232 as a JTAG/SPI/MPSSE Programmer'''
->The Papilio Pro provides the JP4 pin header, jumping this header will hold the Spartan 6 FPGA in a reset state which frees up the JTAG pins to be controlled by the FT2232. OpenOCD, FlashRAM, and any other FT2232 based software should work directly with this method.

[[<<]]

----
[[#PProReset]]
!!!Reset
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:reset-callout.png
%rframe width=300px% [[Attach:reset-schematic.png|Attach:reset-schematic.png]]
Pressing the reset button will cause the Spartan 6 FPGA to do a hard reset and reload the first bit file from SPI Flash. This is a pretty drastic measure that will wipe out anything running on the FPGA. In most cases it is more desirable to utilize a user button to perform a reset within your design that just initializes all registers to zero.
[[<<]]

----
[[#PProUserLED]]
!!!User LED
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:led-callout.png
%rframe height=100px% [[Attach:led-schematic.png|Attach:led-schematic.png]]
The Papilio Pro provides one user LED that is connected directly to the Spartan 6 FPGA. It is not shared with any of the I/O pins and can be controlled directly from your VHDL or sketches.
[[<<]]

----
[[#PProLinks]]
!!!Links
'''Papilio Pro Design Files'''
->[[http://forum.gadgetfactory.net/index.php?/files/getdownload/34-papilio-pro-generic-ucf/|Papilio Pro Generic User Constraint File (UCF)]]
->[[https://github.com/GadgetFactory/Papilio-Pro/archive/master.zip|Papilio Pro EAGLE Design Files]]
->[[https://github.com/GadgetFactory/Papilio-Pro/blob/master/BPC3010_Papilio_Pro.pdf?raw=true|Papilio Pro Schematic (PDF)]]

'''Community Links'''
->[[http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/papilio-pro/|Papilio Pro Project Showcase]]
->[[http://forum.gadgetfactory.net/index.php?/forum/102-papilio-pro-and-papilio-plus/|Papilio Pro Forum]]
->[[http://forum.gadgetfactory.net/index.php?/tags/downloads/papilio+pro/|Papilio Pro Downloads]]

[[<<]]

----
[[#PProLicense]]
!!!License
(:div style='text-align:center; background:#dddddd; border:1px solid #000000; width:100%; padding:5px;':)
%center%[[http://creativecommons.org/licenses/by-nc-sa/3.0/|http://i.creativecommons.org/l/by-nc-sa/3.0/88x31.png]]
Papilio Pro is licensed under a [[http://creativecommons.org/licenses/by-nc-sa/3.0/|Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License]].
Papilio Pro copyright Jack Gassett, Gadget Factory.
(:divend:)
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[[#Images]]
!!!Images
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0' newwin% [[Attach:Papilio pro.png|Attach:Papilio pro.png]]
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0' newwin% [[Attach:papilio pro2.png|Attach:papilio pro2.png]]
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%notetitle% Papilio Pro%%

Click the images for full size hi-resolution views of the Papilio Pro.
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%lframe height=700 width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[https://github.com/GadgetFactory/Papilio-Pro/blob/master/BPC3010_Papilio_Pro.pdf?raw=truee|Attach:ppro-schematic.png]]
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%notetitle% Papilio Pro Schematic%%

Click the image to load a PDF version of the Papilio Pro Schematic
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%lframe width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro-assembly.png|Attach:ppro-assembly.png]]
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%notetitle% Assembly View%%

Click the image for a full size view of the boards part layout.
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