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Papilio: Papilio One Hardware

Hardware | Papilio DUO - Papilio One - Papilio Pro - MegaWings - Wings - Shields

Spartan 3E
Dual Channel USB
SPI Flash

Papilio One

The Papilio is an Open Source FPGA development board based on the Xilinx Spartan 3E FPGA (datasheet). It has 48 I/O lines, dual channel USB, integrated JTAG programmer, 4 power supplies, and a power connector. It provides everything needed to start learning Digital Electronics.




Spartan 3E FPGA

SPI Flash



Xilinx Spartan 3E

The Spartan 3E FPGA used in the Papilio One offers some exciting features:


With the VCCO Select header built into the Papilio voltages of 1.2V, 2.5V, and 3.3V can be used.

Digital Clock Manager (DCM)

Easily generate any clock from 5Mhz to 300Mhz using the DCM clock wizard. 4 DCM's allow you to generate many clocks from the external 32Mhz Oscillator included on the Papilio One board.

FPGA Schematic

Multiple Signal Standards

LVCMOS, LVTTL, HSTL, differential pairs for LVDS, mini-LVDS

Boot from SPI Flash

The Spartan 3E boots from an industry standard SPI Flash device included on the Papilio One board.

BRAM Memory Blocks

The Spartan 3E includes fast, dual-port, internal SRAM called Block RAM.
Papilio Board18Kbit BRAM BlocksMax SRAMUsable SRAM
Papilio Pro32576Kbit (72KByte)512Kbit (64KByte)
Papilio One 500K20360Kbit (45KByte)320Kbit (40KByte)
Papilio One 250K12216Kbit (27KByte)192Kbit (24KByte)

BRAM's are 18Kbit in size including two parity bits. In most cases the two parity bits are not used so the BRAM's usable size becomes 16Kbit. If your design can use an 18 bit wide bus then it is possible to utilize the parity bits for data and gain access to all 18Kbit memory space.


The Papilio One can be powered from the USB connector, an external power supply, or a battery. The PWRSELECT jumper controls whether the USB connector or the Power Jack/PWRIN connectors are active.

Power Selection

When the USB connector is selected up to 500mA of current is supplied to the 1.2V, 2.5V, and 3.3V LD1117 voltage regulators. The 5V power rail is supplied directly by the USB port and the 5V LD1117 power regulator is inactive.
When the power jack or battery is selected the 5V LD1117 voltage regulator supplies up to 800mA of current to the 1.2V, 2.5V, and 3.3V LD1117 voltage regulators. The power jack or battery must provide at least 6V in order to generate the desired 5V output.

Power Schematic

Power Jack


The JTAG programming pins on the Spartan 3E always operate at 2.5V while the connected JTAG pins of the FT2232D always operate at 3.3V. This difference in voltage can cause the Spartan 3E to send reverse current back on the 2.5V power rail. The RPAR resistor provides a shunt for this reverse current to be dissipated. The Xilinx application notes recommend the use of RPAR in the case that a voltage regulator cannot handle reverse current. The LD1117 datasheet does not indicate that it can handle reverse current so RPAR was included. Testing has shown that the LD1117 seems to handle the reverse current just fine but boards will be populated with RPAR as a safety precaution. The RPAR resistor consumes 25mA of current so if a battery is being used it is recommended to remove the RPAR resistor to help extend battery life. Please understand that the possible effects of removing the RPAR resistor are the 2.5V rail going higher than 2.5V and possibly damaging the 2.5V voltage regulator. There is an interesting discussion about the need for RPAR here.

Dual Channel USB

The Papilio One uses the FT2232 dual channel USB chip for JTAG programming and Serial UART communications.

USB Schematic

NameDirection (FPGA Perspective)FunctionArduino PinPapilio Wing PinPapilio One Pin
RXInputFPGA Serial Receive (MISO)N/AN/AP88
TXOutputFPGA Serial Transmit (MOSI)N/AN/AP90

SPI Flash

The 4Mbit SST SST25VF040B SPI Flash chip provides plenty of space for a boot bit file and user data. Any bit file written to SPI Flash using the Papilio Loader tool will automatically startup when power is applied.

NameDirection (FPGA Perspective)FunctionArduino PinPapilio Wing PinPapilio One Pin
FLASH_CSOutputSPI Flash Chip SelectN/AN/AP24
FLASH_CLKOutputSPI Flash ClockN/AN/AP50
FLASH_MOSIOutputSPI Flash Master Out Slave In (MOSI)N/AN/AP27
FLASH_MISOInputSPI Flash Master In Slave Out (MISO)N/AN/AP44


I/O Blocks

The I/O blocks provides programmable interface between pins and the Spartan-3E internal logic.

I/O Banks

The VCCO jumper selects the voltage for all of the I/O lines, the options are 1.2V, 2.5V, and 3.3V. The recommended setting is 3.3V since most peripherals operate at 3.3V.


The Papilio One has a 32Mhz oscillator that can be converted to any speed desired inside the FPGA using the Digital Clock Manager (DCM). There are four Digital Clock Managers (DCM) available for your designs.

NameDirection (FPGA Perspective)FunctionArduino PinPapilio Wing PinPapilio One Pin
CLKInputExternal 32Mhz OscillatorN/AN/AP89


The JTAG header on the Papilio One is provided so external JTAG programmers can be used:

Use a Xilinx Programming Cable

If you want to use the Xilinx tools such as EDK, Chipscope, or Impact with the Papilio you need a way to use a Xilinx programming cable. The Papilio has a Xilinx JTAG header but the problem is that in the default mode the FT2232D USB chip is connected to the JTAG pins and interferes with programming. What is needed is to put the FT2232 into a mode where the JTAG pins go into High-Z leaving the Xilinx JTAG pins free for the programming cable. To learn more about using a Xilinx Programming Cable visit the original forum post or blog post.

NameDirection (FPGA Perspective)FunctionArduino PinPapilio Wing PinPapilio One Pin


The Papilio One has a power LED, a RX LED, and a TX LED. The power led lights up to indicate that power is being supplied to the board while the RX and TX led's show UART traffic.


Papilio One Design Files
Community Links


Papilio One is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License.
Papilio One copyright Jack Gassett, Gadget Factory.


Papilio One

Click the images for full size hi-resolution views of the Papilio One.

Papilio Pro Schematic

Click the image to load a PDF version of the Papilio One Schematic

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Page last modified on February 12, 2015, at 01:32 PM