Papilio.PapilioOne History

Hide minor edits - Show changes to output

Changed lines 226-228 from:
-->[[http://forum.gadgetfactory.net/index.php?/files/file/13-eagle-files/|Papilio One EAGLE Design Files (License CC-BY-SA-NC)]]
-->[[http://gadgetforge.gadgetfactory.net/gf/download/docmanfileversion/8/455/Butterfly_One_Schematic.pdf|Papilio One Schematic (PDF)]]
to:
-->[[http://papilio.cc/uploads/Papilio/BPC3003_Papilio_One_v2.04.zip|Papilio One EAGLE Design Files (License CC-BY-SA-NC)]]
-->[[http://papilio.cc/uploads/Papilio/Butterfly_One.pdf|Papilio One Schematic (PDF)]]
Changed line 262 from:
%lframe height=700 width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[http://gadgetforge.gadgetfactory.net/gf/download/docmanfileversion/8/455/Butterfly_One_Schematic.pdf|Attach:schematicall.png]]
to:
%lframe height=700 width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[http://papilio.cc/uploads/Papilio/Butterfly_One.pdf|Attach:schematicall.png]]
Changed line 268 from:
[[<<]]
to:
[[<<]]
Changed line 123 from:
->The JTAG programming pins on the Spartan 3E always operate at 2.5V while the connected JTAG pins of the FT2232D always operate at 3.3V. This difference in voltage can cause the Spartan 3E to send reverse current back on the 2.5V power rail. The RPAR resistor provides a shunt for this reverse current to be dissipated. The Xilinx application notes recommend the use of RPAR in the case that a voltage regulator cannot handle reverse current. The LD1117 datasheet does not indicate that it can handle reverse current so RPAR was included. Testing has shown that the LD1117 seems to handle the reverse current just fine but boards will be populated with RPAR as a safety precaution. For more safety, you can store this inter into a [[http://www.infosafe.fr/coffre-fort-ignifuge/coffre-fort-ignifuge.htm small fireproof safe]]. The RPAR resistor consumes 25mA of current so if a battery is being used it is recommended to remove the RPAR resistor to help extend battery life. Please understand that the possible effects of removing the RPAR resistor are the 2.5V rail going higher than 2.5V and possibly damaging the 2.5V voltage regulator. There is an interesting discussion about the need for RPAR [[http://newsgroups.derkeiler.com/Archive/Comp/comp.arch.fpga/2008-03/msg00659.html|here]].
to:
->The JTAG programming pins on the Spartan 3E always operate at 2.5V while the connected JTAG pins of the FT2232D always operate at 3.3V. This difference in voltage can cause the Spartan 3E to send reverse current back on the 2.5V power rail. The RPAR resistor provides a shunt for this reverse current to be dissipated. The Xilinx application notes recommend the use of RPAR in the case that a voltage regulator cannot handle reverse current. The LD1117 datasheet does not indicate that it can handle reverse current so RPAR was included. Testing has shown that the LD1117 seems to handle the reverse current just fine but boards will be populated with RPAR as a safety precaution. The RPAR resistor consumes 25mA of current so if a battery is being used it is recommended to remove the RPAR resistor to help extend battery life. Please understand that the possible effects of removing the RPAR resistor are the 2.5V rail going higher than 2.5V and possibly damaging the 2.5V voltage regulator. There is an interesting discussion about the need for RPAR [[http://newsgroups.derkeiler.com/Archive/Comp/comp.arch.fpga/2008-03/msg00659.html|here]].
Changed line 123 from:
->The JTAG programming pins on the Spartan 3E always operate at 2.5V while the connected JTAG pins of the FT2232D always operate at 3.3V. This difference in voltage can cause the Spartan 3E to send reverse current back on the 2.5V power rail. The RPAR resistor provides a shunt for this reverse current to be dissipated. The Xilinx application notes recommend the use of RPAR in the case that a voltage regulator cannot handle reverse current. The LD1117 datasheet does not indicate that it can handle reverse current so RPAR was included. Testing has shown that the LD1117 seems to handle the reverse current just fine but boards will be populated with RPAR as a safety precaution. The RPAR resistor consumes 25mA of current so if a battery is being used it is recommended to remove the RPAR resistor to help extend battery life. Please understand that the possible effects of removing the RPAR resistor are the 2.5V rail going higher than 2.5V and possibly damaging the 2.5V voltage regulator. There is an interesting discussion about the need for RPAR [[http://newsgroups.derkeiler.com/Archive/Comp/comp.arch.fpga/2008-03/msg00659.html|here]].
to:
->The JTAG programming pins on the Spartan 3E always operate at 2.5V while the connected JTAG pins of the FT2232D always operate at 3.3V. This difference in voltage can cause the Spartan 3E to send reverse current back on the 2.5V power rail. The RPAR resistor provides a shunt for this reverse current to be dissipated. The Xilinx application notes recommend the use of RPAR in the case that a voltage regulator cannot handle reverse current. The LD1117 datasheet does not indicate that it can handle reverse current so RPAR was included. Testing has shown that the LD1117 seems to handle the reverse current just fine but boards will be populated with RPAR as a safety precaution. For more safety, you can store this inter into a [[http://www.infosafe.fr/coffre-fort-ignifuge/coffre-fort-ignifuge.htm small fireproof safe]]. The RPAR resistor consumes 25mA of current so if a battery is being used it is recommended to remove the RPAR resistor to help extend battery life. Please understand that the possible effects of removing the RPAR resistor are the 2.5V rail going higher than 2.5V and possibly damaging the 2.5V voltage regulator. There is an interesting discussion about the need for RPAR [[http://newsgroups.derkeiler.com/Archive/Comp/comp.arch.fpga/2008-03/msg00659.html|here]].
Changed line 123 from:
->The JTAG programming pins on the Spartan 3E always operate at 2.5V while the connected JTAG pins of the FT2232D always operate at 3.3V. This difference in voltage can cause the Spartan 3E to send reverse current back on the 2.5V power rail. The RPAR resistor provides a shunt for this reverse current to be dissipated. The Xilinx application notes recommend the use of RPAR in the case that a voltage regulator cannot handle reverse current. The LD1117 datasheet does not indicate that it can handle reverse current so RPAR was included. Testing has shown that the LD1117 seems to handle the reverse current just fine but boards will be populated with RPAR as a safety precaution. For more safety, you can store this inter into a [[http://www.infosafe.fr/coffre-fort-ignifuge/coffre-fort-ignifuge.htm small fireproof safe]]. The RPAR resistor consumes 25mA of current so if a battery is being used it is recommended to remove the RPAR resistor to help extend battery life. Please understand that the possible effects of removing the RPAR resistor are the 2.5V rail going higher than 2.5V and possibly damaging the 2.5V voltage regulator. There is an interesting discussion about the need for RPAR [[http://newsgroups.derkeiler.com/Archive/Comp/comp.arch.fpga/2008-03/msg00659.html|here]].
to:
->The JTAG programming pins on the Spartan 3E always operate at 2.5V while the connected JTAG pins of the FT2232D always operate at 3.3V. This difference in voltage can cause the Spartan 3E to send reverse current back on the 2.5V power rail. The RPAR resistor provides a shunt for this reverse current to be dissipated. The Xilinx application notes recommend the use of RPAR in the case that a voltage regulator cannot handle reverse current. The LD1117 datasheet does not indicate that it can handle reverse current so RPAR was included. Testing has shown that the LD1117 seems to handle the reverse current just fine but boards will be populated with RPAR as a safety precaution. The RPAR resistor consumes 25mA of current so if a battery is being used it is recommended to remove the RPAR resistor to help extend battery life. Please understand that the possible effects of removing the RPAR resistor are the 2.5V rail going higher than 2.5V and possibly damaging the 2.5V voltage regulator. There is an interesting discussion about the need for RPAR [[http://newsgroups.derkeiler.com/Archive/Comp/comp.arch.fpga/2008-03/msg00659.html|here]].
Changed line 123 from:
->The JTAG programming pins on the Spartan 3E always operate at 2.5V while the connected JTAG pins of the FT2232D always operate at 3.3V. This difference in voltage can cause the Spartan 3E to send reverse current back on the 2.5V power rail. The RPAR resistor provides a shunt for this reverse current to be dissipated. The Xilinx application notes recommend the use of RPAR in the case that a voltage regulator cannot handle reverse current. The LD1117 datasheet does not indicate that it can handle reverse current so RPAR was included. Testing has shown that the LD1117 seems to handle the reverse current just fine but boards will be populated with RPAR as a safety precaution. The RPAR resistor consumes 25mA of current so if a battery is being used it is recommended to remove the RPAR resistor to help extend battery life. Please understand that the possible effects of removing the RPAR resistor are the 2.5V rail going higher than 2.5V and possibly damaging the 2.5V voltage regulator. There is an interesting discussion about the need for RPAR [[http://newsgroups.derkeiler.com/Archive/Comp/comp.arch.fpga/2008-03/msg00659.html|here]].
to:
->The JTAG programming pins on the Spartan 3E always operate at 2.5V while the connected JTAG pins of the FT2232D always operate at 3.3V. This difference in voltage can cause the Spartan 3E to send reverse current back on the 2.5V power rail. The RPAR resistor provides a shunt for this reverse current to be dissipated. The Xilinx application notes recommend the use of RPAR in the case that a voltage regulator cannot handle reverse current. The LD1117 datasheet does not indicate that it can handle reverse current so RPAR was included. Testing has shown that the LD1117 seems to handle the reverse current just fine but boards will be populated with RPAR as a safety precaution. For more safety, you can store this inter into a [[http://www.infosafe.fr/coffre-fort-ignifuge/coffre-fort-ignifuge.htm small fireproof safe]]. The RPAR resistor consumes 25mA of current so if a battery is being used it is recommended to remove the RPAR resistor to help extend battery life. Please understand that the possible effects of removing the RPAR resistor are the 2.5V rail going higher than 2.5V and possibly damaging the 2.5V voltage regulator. There is an interesting discussion about the need for RPAR [[http://newsgroups.derkeiler.com/Archive/Comp/comp.arch.fpga/2008-03/msg00659.html|here]].
Changed line 49 from:
* EEPROM memory to store configuration settings for [[http://www.ftdichip.com/Documents/DataSheets/DS_FT2232D.pdf|FT2232]] USB chip.
to:
* EEPROM memory to store configuration settings for [[http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232D.pdf|FT2232]] USB chip.
September 13, 2013, at 11:14 PM by guanucoluis - I changed the channel definitions on FT2232D. The channel A has MPSSE engine
Changed lines 133-134 from:
*Channel A is connected to the Papilio One in an Asynchronous serial UART configuration that is capable of speeds up to 2MHz.
*Channel B is connected to the JTAG pins of the Papilio One and provides very fast programming of the FPGA (500mS).
to:
*Channel A is connected to the JTAG pins of the Papilio One and provides very fast programming of the FPGA (500mS).
*Channel B is connected to the Papilio One in an Asynchronous serial UART configuration that is capable of speeds up to 2MHz.
May 10, 2013, at 11:13 AM by Jack Gassett -
Changed line 266 from:
Click the image to load a PDF version of the Papilio Pro Schematic
to:
Click the image to load a PDF version of the Papilio One Schematic
May 10, 2013, at 11:12 AM by Jack Gassett -
Changed lines 20-22 from:
[[#Section8|Section Name]][[<<]]
[[#Section9|Section Name]][[<<]]
[[#Section10|Section Name
]][[<<]]
to:
[[#Section8|LEDs]][[<<]]
May 10, 2013, at 11:11 AM by Jack Gassett -
Changed line 264 from:
%lframe height=700 width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[https://github.com/GadgetFactory/Papilio-Pro/blob/master/BPC3010_Papilio_Pro.pdf?raw=truee|Attach:ppro-schematic.png]]
to:
%lframe height=700 width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[http://gadgetforge.gadgetfactory.net/gf/download/docmanfileversion/8/455/Butterfly_One_Schematic.pdf|Attach:schematicall.png]]
Deleted lines 270-280:

%lframe width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro-assembly.png|Attach:ppro-assembly.png]]
>>postit<<
%notetitle% Assembly View%%

Click the image for a full size view of the boards part layout.
>><<
[[<<]]

!!! License
* [[http://gadgetforge.gadgetfactory.net/gf/download/frsrelease/142/460/BPC3003_Papilio_One_v2.04.zip|All design files are available under a Completely Open Source Creative Commons Attribution Non-Commercial.]]
May 10, 2013, at 11:07 AM by Jack Gassett -
Changed lines 18-19 from:
[[#Section6|Section Name]][[<<]]
[[#Section7|Section Name]][[<<]]
to:
[[#Section6|Oscillator]][[<<]]
[[#Section7|JTAG]][[<<]]
Changed lines 218-222 from:



!!! LED's
to:
----
[[#Section8]]
!!!LED's
Changed lines 222-234 from:
!!Quick Links
[[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|Xilinx Spartan-3E datasheet]]

[[http://gadgetforge.gadgetfactory.net/gf/download/frsrelease/134/412/BPC3003_2.03%2B.ucf|Xilinx UFC file]]

[[http://www.gadgetfactory.net/blog/wp-content/uploads/2011/02/Papilio_Pins.png|Pin mapping]]

[[http://gadgetforge.gadgetfactory.net/gf/download/docmanfileversion/8/455/Butterfly_One_Schematic.pdf|Schematic]]

[[http://gadgetforge.gadgetfactory.net/gf/download/frsrelease/142/460/BPC3003_Papilio_One_v2.04.zip|EAGLE files (License CC-BY-SA-NC)]]

!! Specifications
to:
----
[[#Links]]
!!!Links
->'''Papilio One Design Files'''
-->
[[http://forum.gadgetfactory.net/index.php?/files/file/2-papilio-one-generic-ucf/|Papilio One Generic User Constraint File (UCF)]]
-->[[http://forum.gadgetfactory.net/index.php?/files/file/13-eagle-files/|Papilio One EAGLE Design Files (License CC-BY-SA-NC)]]
-->
[[http://gadgetforge.gadgetfactory.net/gf/download/docmanfileversion/8/455/Butterfly_One_Schematic.pdf|Papilio One Schematic (PDF)]]

->'''Community Links'''
-->
[[http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/papilio-one/|Papilio One Project Showcase]]
-->[[http://forum.gadgetfactory.net/index.php?/forum/89-papilio-one/|Papilio One Forum]]
-->[[http://forum.gadgetfactory.net/index.php?/files/category/3-papilio-one/|Papilio One Downloads]]

->'''Misc'''
-->[[http://www.gadgetfactory.net/blog/wp-content/uploads/2011/02/Papilio_Pins.png|Pin mapping]]
-->[[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|Xilinx Spartan-3E datasheet]]

[[<<]]
----
[[#License]]
!!!License
(:div style='text-align:center; background:#dddddd; border:1px solid #000000; width:100%; padding:5px;':)
%center%[[http://creativecommons.org/licenses/by-nc-sa/3.0/|http://i.creativecommons.org/l/by-nc-sa/3.0/88x31.png]]
Papilio One is licensed under a [[http://creativecommons.org/licenses/by-nc-sa/3.0/|Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License]].
\\
Papilio One copyright Jack Gassett, Gadget Factory.
(:divend:)
[[<<]]

----
[[#Images]]
!!!Images
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0' newwin% [[Attach:PapilioOne.png|Attach:PapilioOne.png]]
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0' newwin% [[Attach:papilioOne2.png|Attach:papilioOne2.png]]
>>postit<<
%notetitle% Papilio One%%

Click the images for full size hi-resolution views of the Papilio One.
>><<
[[<<]]

%lframe height=700 width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[https://github.com/GadgetFactory/Papilio-Pro/blob/master/BPC3010_Papilio_Pro.pdf?raw=truee|Attach:ppro-schematic.png]]
>>postit<<
%notetitle% Papilio Pro Schematic%%

Click the image to load a PDF version of the Papilio Pro Schematic
>><<
[[<<]]

%lframe width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro-assembly.png|Attach:ppro-assembly.png]]
>>postit<<
%notetitle% Assembly View%%

Click the image for a full size view of the boards part layout.
>><<
[[<<]]
May 10, 2013, at 10:54 AM by Jack Gassett -
Changed lines 185-199 from:
to:
----
[[#Section6]]
!!!Oscillator
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:osc-callout.png
%rframe width=300px% [[Attach:osc-schematic.png|Attach:osc-schematic.png]]
The Papilio One has a 32Mhz oscillator that can be converted to any speed desired inside the FPGA using the Digital Clock Manager (DCM). There are four [[http://www.papilio.cc/index.php?n=Papilio.DigitalClockManager|Digital Clock Managers (DCM)]] available for your designs.
[[<<]]

|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio One Pin||
||CLK||Input||External 32Mhz Oscillator||N/A||N/A||P89||
\\

----
[[#Section7]]
Changed lines 201-214 from:
The Xilinx device is programmed using any application that can support the FT2232D MPSSE JTAG mode. The [[http://gadgetforge.gadgetfactory.net/gf/project/butterflyloader/|Papilio Loader]] is one such application.

!!!JTAG Programming Port
The JTAG programming port is included for use with external JTAG programmers such as the Xilinx JTAG cables. The
Xilinx tools such as Impact and the EDK do not support FT2232D based programmers nor does Xilinx provide any method to add support for non-Xilinx programmers. This external port is provided as a means to use the Xilinx tools with the Papilio One. The Xilinx tools can still be used without an Xilinx programmer by generating bitstreams that can be loaded by the Papilio Loader.

TEMPORARY LIMITATION: In order to use
the external JTAG port the FT2232D lines that are connected to the JTAG port need to be put into a HIGH-Z state. This has not been tested yet and will probably require a special application.

!!!EEPROM
Custom VID
/PID and configuration data can be loaded into the provided EEPROM using the [[http://ftdichip.com/Resources/Utilities.htm#MProg|FTDI MProg]] application.


!! Misc
!!! Oscillator
The Papilio One has a 32Mhz oscillator that can be converted to any speed desired inside the FPGA using a [[Papilio.DigitalClockManager
|Digital Clock Manager]]. The Spartan 3E provides 4 Digital Clock Managers.
to:
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:jtag-callout.png
%rframe width=200px%
[[Attach:jtag-schematic.png|Attach:jtag-schematic.png]]
The JTAG header on the Papilio One is provided so external JTAG programmers can be used:

'''Use a Xilinx Programming Cable'''
->If you want to use the
Xilinx tools such as EDK, Chipscope, or Impact with the Papilio you need a way to use a Xilinx programming cable. The Papilio has a Xilinx JTAG header but the problem is that in the default mode the FT2232D USB chip is connected to the JTAG pins and interferes with programming. What is needed is to put the FT2232 into a mode where the JTAG pins go into High-Z leaving the Xilinx JTAG pins free for the programming cable. To learn more about using a Xilinx Programming Cable visit the [[http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/xilinx-programming-cable-with-papilio-r39|original forum post]] or [[http://www.gadgetfactory.net/2012/09/use-a-xilinx-programming-cable-with-the-papilio/|blog post]].

[[<<]]

|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio One Pin||
||JTAG_TMS||Input||JTAG TMS
||N/A||N/A||P75||
||JTAG_TCK||Input||JTAG TCK||N/A||N/A||P77||
||JTAG_SI||Input||JTAG SI||N/A||N/A||P100||
||JTAG_SO||Output||JTAG SO||N/A||N/A||P76||
\\


May 10, 2013, at 10:49 AM by Jack Gassett -
Deleted line 169:
%rframe height=250px% [[Attach:schematic5.png|Attach:schematic5.png]]
Added lines 181-182:
%rframe height=250px% [[Attach:schematic5.png|Attach:schematic5.png]]
Deleted lines 184-193:
!! Memory
The on-board SPI Flash provides 4Mbits of space to store a bitstream that is loaded by the FPGA at start-up. Bitstreams are loaded to SPI Flash using the [[Papilio Loader]].

!! Communications
The Papilio One uses a [[http://www.ftdichip.com/Documents/DataSheets/DS_FT2232D.pdf|FTDI 2232D]] USB chip which provides two channels over one USB connection. One of the channels is configured as a simple UART device and shows up as a virtual COM port. The other channel takes advantage of the MPSSE (Multi-Protocol Synchronous Serial Engine) functionality to implement a high speed JTAG channel for programming the [[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|Xilinx Spartan 3E]].
!!!Drivers
The first time the Papilio One is plugged into the computer it will be necessary to install the FTDI device drivers. [[http://ftdichip.com/Drivers/D2XX.htm|Drivers can be downloaded from the FTDI website]].

!!!UART
When the Papilio One is plugged into the USB port both channels will be detected and will show up under the Control Panel as a virtual COM port. The second virtual COM port is the UART channel.
May 10, 2013, at 10:46 AM by Jack Gassett -
Changed line 17 from:
[[#Section5|Section Name]][[<<]]
to:
[[#Section5|I/O]][[<<]]
Changed lines 166-170 from:
!!Inputs/Outputs
!!!I/
O Blocks
The I/O blocks provides programmable interface between pins and the Spartan-3E internal logic
.
*Features
:
to:
----
[[#Section5]]
!!!I/O
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:io-callout.png
%rframe height=250px% [[Attach:schematic5
.png|Attach:schematic5.png]]
'''I/O Blocks'''
->The I/O blocks provides programmable interface between pins and the Spartan-3E internal logic.
Changed lines 178-180 from:
!!!I/O Banks
*The VCCO jumper selects the voltage for all of the I/O lines, the options are 1.2V, 2.5V, and 3.3V. The recommended setting is 3.3V since most peripherals operate at 3.3V.
to:
'''I/O Banks'''
->
The VCCO jumper selects the voltage for all of the I/O lines, the options are 1.2V, 2.5V, and 3.3V. The recommended setting is 3.3V since most peripherals operate at 3.3V.

[[<<]]
May 10, 2013, at 10:41 AM by Jack Gassett -
Changed lines 15-16 from:
[[#Section3|USB]][[<<]]
[[#Section4|Section Name]][[<<]]
to:
[[#Section3|Dual Channel USB]][[<<]]
[[#Section4|SPI Flash]][[<<]]
Added lines 150-164:
----
[[#Section4]]
!!!SPI Flash
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:flash-callout.png
%rframe width=300px% [[Attach:flash-schematic.png|Attach:flash-schematic.png]]
The 4Mbit SST %newwin%[[http://ww1.microchip.com/downloads/en/DeviceDoc/25051A.pdf|SST25VF040B]] SPI Flash chip provides plenty of space for a boot bit file and user data. Any bit file written to SPI Flash using the [[Papilio.PapilioLoaderV2|Papilio Loader]] tool will automatically startup when power is applied.
[[<<]]

|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio One Pin||
||FLASH_CS||Output||SPI Flash Chip Select||N/A||N/A||P24||
||FLASH_CLK||Output||SPI Flash Clock||N/A||N/A||P50||
||FLASH_MOSI||Output||SPI Flash Master Out Slave In (MOSI)||N/A||N/A||P27||
||FLASH_MISO||Input||SPI Flash Master In Slave Out (MISO)||N/A||N/A||P44||
\\
May 10, 2013, at 10:30 AM by Jack Gassett -
Changed line 15 from:
[[#Section3|Section Name]][[<<]]
to:
[[#Section3|USB]][[<<]]
Added lines 128-150:

----
[[#Section3]]
!!!Dual Channel USB
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:usb-callout.png
The Papilio One uses the %newwin%[[http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232D.pdf|FT2232]] dual channel USB chip for JTAG programming and Serial UART communications.

*Channel A is connected to the Papilio One in an Asynchronous serial UART configuration that is capable of speeds up to 2MHz.
*Channel B is connected to the JTAG pins of the Papilio One and provides very fast programming of the FPGA (500mS).
[[<<]]


%cframe text-align=center width=500% [[Attach:usb-schematic.png|Attach:usb-schematic.png]]|'''USB Schematic'''
[[<<]]


|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio One Pin||
||RX||Input||FPGA Serial Receive (MISO)||N/A||N/A||P88||
||TX||Output||FPGA Serial Transmit (MOSI)||N/A||N/A||P90||
\\
May 10, 2013, at 10:25 AM by Jack Gassett -
Changed line 14 from:
[[#Section2|Section Name]][[<<]]
to:
[[#Section2|Power]][[<<]]
Changed line 116 from:
%rframe text-align=center width=200px% [[Attach:schematic2.png|Attach:schematic2.png]]|'''Power Schematic'''
to:
%rframe text-align=center width=350px% [[Attach:schematic2.png|Attach:schematic2.png]]|'''Power Schematic'''
May 10, 2013, at 10:22 AM by Jack Gassett -
Changed lines 105-118 from:
!!Inputs/Outputs
!!!I/O Blocks
The I/O blocks provides programmable interface between pins and the Spartan-3E internal logic
.
*Features:
**Programmable pull-down, pull-up and float resistors (Pull-down by default on unused pins).
**Programmable input delay.
**Optional keeper circuit (keeps last logic level, see spartan-3E datasheet page 18).
** 2 to 16 mA programmable output current drive strength.
**All I/O pins are in high-impedance state during configuration (program loading). Unused pins are pull-down inputs by default with the Xilinx ISE software.
!!!I/O Banks
*The VCCO jumper selects the voltage for all of the I/O lines, the options are 1.2V, 2.5V, and 3.3V. The recommended setting is 3.3V since most peripherals operate at 3.3V.

!! Power
to:
----
[[#Section2]]
!!!Power
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:callout2
.png
Changed lines 111-122 from:
!!! Power Selection

When the USB connector is selected up to 500mA of current is supplied to the 1.2V, 2.5V, and 3.3V LD1117 voltage regulators. The 5V power rail is supplied directly by the USB port and the 5V LD1117 power regulator is inactive.

When the power jack or battery is selected the 5V LD1117 voltage regulator supplies up to 800mA of current to the 1.2V, 2.5V, and 3.3V LD1117 voltage regulators. The power jack or battery must provide at least 6V in order to generate the desired 5V output.

!!! RPAR

The JTAG programming pins on the Spartan 3E always operate at 2
.5V while the connected JTAG pins of the FT2232D always operate at 3.3V. This difference in voltage can cause the Spartan 3E to send reverse current back on the 2.5V power rail. The RPAR resistor provides a shunt for this reverse current to be dissipated. The Xilinx application notes recommend the use of RPAR in the case that a voltage regulator cannot handle reverse current. The LD1117 datasheet does not indicate that it can handle reverse current so RPAR was included. Testing has shown that the LD1117 seems to handle the reverse current just fine but boards will be populated with RPAR as a safety precaution. The RPAR resistor consumes 25mA of current so if a battery is being used it is recommended to remove the RPAR resistor to help extend battery life. Please understand that the possible effects of removing the RPAR resistor are the 2.5V rail going higher than 2.5V and possibly damaging the 2.5V voltage regulator. There is an interesting discussion about the need for RPAR [[http://newsgroups.derkeiler.com/Archive/Comp/comp.arch.fpga/2008-03/msg00659.html|here]].

!!! Power
Jack
to:
'''Power Selection'''
->
When the USB connector is selected up to 500mA of current is supplied to the 1.2V, 2.5V, and 3.3V LD1117 voltage regulators. The 5V power rail is supplied directly by the USB port and the 5V LD1117 power regulator is inactive.

-> When the power jack or battery is selected the 5V LD1117 voltage regulator supplies up to 800mA of current to the 1.2V, 2.5V, and 3.3V LD1117 voltage regulators. The power jack or battery must provide at least 6V in order to generate the desired 5V output.

%rframe text-align=center width=200px% [[Attach:schematic2.png|Attach:schematic2.png]]|'''Power Schematic'''

'''Power
Jack'''
Added lines 123-140:

'''RPAR'''
->The JTAG programming pins on the Spartan 3E always operate at 2.5V while the connected JTAG pins of the FT2232D always operate at 3.3V. This difference in voltage can cause the Spartan 3E to send reverse current back on the 2.5V power rail. The RPAR resistor provides a shunt for this reverse current to be dissipated. The Xilinx application notes recommend the use of RPAR in the case that a voltage regulator cannot handle reverse current. The LD1117 datasheet does not indicate that it can handle reverse current so RPAR was included. Testing has shown that the LD1117 seems to handle the reverse current just fine but boards will be populated with RPAR as a safety precaution. The RPAR resistor consumes 25mA of current so if a battery is being used it is recommended to remove the RPAR resistor to help extend battery life. Please understand that the possible effects of removing the RPAR resistor are the 2.5V rail going higher than 2.5V and possibly damaging the 2.5V voltage regulator. There is an interesting discussion about the need for RPAR [[http://newsgroups.derkeiler.com/Archive/Comp/comp.arch.fpga/2008-03/msg00659.html|here]].

[[<<]]

!!Inputs/Outputs
!!!I/O Blocks
The I/O blocks provides programmable interface between pins and the Spartan-3E internal logic.
*Features:
**Programmable pull-down, pull-up and float resistors (Pull-down by default on unused pins).
**Programmable input delay.
**Optional keeper circuit (keeps last logic level, see spartan-3E datasheet page 18).
** 2 to 16 mA programmable output current drive strength.
**All I/O pins are in high-impedance state during configuration (program loading). Unused pins are pull-down inputs by default with the Xilinx ISE software.
!!!I/O Banks
*The VCCO jumper selects the voltage for all of the I/O lines, the options are 1.2V, 2.5V, and 3.3V. The recommended setting is 3.3V since most peripherals operate at 3.3V.
May 10, 2013, at 10:17 AM by Jack Gassett -
Changed line 73 from:
The Spartan 3E used in the Papilio One offers some exciting features:
to:
The [[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|Spartan 3E FPGA]] used in the Papilio One offers some exciting features:
May 10, 2013, at 10:16 AM by Jack Gassett -
Changed lines 81-83 from:
%rframe text-align=center width=200px% [[Attach:schematic1.png|Attach:schematic1.png]]|'''FPGA Schematic'''
\\
\\
to:
%rframe text-align=center width=300px% [[Attach:schematic1.png|Attach:schematic1.png]]|'''FPGA Schematic'''
May 10, 2013, at 10:15 AM by Jack Gassett -
Changed line 13 from:
[[#Section1|Section Name]][[<<]]
to:
[[#Section1|Spartan 3E]][[<<]]
Added lines 78-80:
'''Digital Clock Manager (DCM)'''
->Easily generate any clock from 5Mhz to 300Mhz using the DCM clock wizard. 4 DCM's allow you to generate many clocks from the external 32Mhz Oscillator included on the Papilio One board.
Deleted lines 83-85:

'''Digital Clock Manager (DCM)'''
->Easily generate any clock from 5Mhz to 300Mhz using the DCM clock wizard. 4 DCM's allow you to generate many clocks from the external 32Mhz Oscillator included on the Papilio One board.
May 10, 2013, at 10:13 AM by Jack Gassett -
Changed lines 69-105 from:
to:
----
[[#Section1]]
!!!Xilinx Spartan 3E
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:callout1.png
The Spartan 3E used in the Papilio One offers some exciting features:

'''Multi-Voltage'''
->With the VCCO Select header built into the Papilio voltages of 1.2V, 2.5V, and 3.3V can be used.

%rframe text-align=center width=200px% [[Attach:schematic1.png|Attach:schematic1.png]]|'''FPGA Schematic'''
\\
\\

'''Digital Clock Manager (DCM)'''
->Easily generate any clock from 5Mhz to 300Mhz using the DCM clock wizard. 4 DCM's allow you to generate many clocks from the external 32Mhz Oscillator included on the Papilio One board.

'''Multiple Signal Standards'''
->LVCMOS, LVTTL, HSTL, differential pairs for LVDS, mini-LVDS

'''Boot from SPI Flash'''
->The Spartan 3E boots from an industry standard SPI Flash device included on the Papilio One board.

'''BRAM Memory Blocks'''
->The Spartan 3E includes fast, dual-port, internal SRAM called Block RAM.

||class=prettytable3
||Papilio Board||18Kbit BRAM Blocks||Max SRAM||Usable SRAM||
||Papilio Pro||32||576Kbit (72KByte)||512Kbit (64KByte)||
||Papilio One 500K||20||360Kbit (45KByte)||320Kbit (40KByte)||
||Papilio One 250K||12||216Kbit (27KByte)||192Kbit (24KByte)
\\

>>important<<
BRAM's are 18Kbit in size including two parity bits. In most cases the two parity bits are not used so the BRAM's usable size becomes 16Kbit. If your design can use an 18 bit wide bus then it is possible to utilize the parity bits for data and gain access to all 18Kbit memory space.
>><<

[[<<]]
May 10, 2013, at 09:50 AM by Jack Gassett -
Changed line 48 from:
** Input Voltage (recommended): 6.5-15V
to:
** Input Voltage (recommended): 6.5-10V
May 10, 2013, at 09:49 AM by Jack Gassett -
Changed lines 42-43 from:
*Features List
to:
!!!Features
>>lrindent round frame<<
Changed line 57 from:
* 4M SPI Flash for [[design persistence]].
to:
* 4M SPI Flash
Changed lines 67-86 from:


!!Quick Links
[[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|Xilinx Spartan-3E datasheet]]

[[http://gadgetforge.gadgetfactory.net/gf/download/frsrelease/134/412/BPC3003_2.03%2B.ucf|Xilinx UFC file]]

[[http://www.gadgetfactory.net/blog/wp-content/uploads/2011/02/Papilio_Pins.png|Pin mapping]]

[[http://gadgetforge.gadgetfactory.net/gf/download/docmanfileversion/8/455/Butterfly_One_Schematic.pdf|Schematic]]

[[http://gadgetforge.gadgetfactory.net/gf/download/frsrelease/142/460/BPC3003_Papilio_One_v2.04.zip|EAGLE files (License CC-BY-SA-NC)]]

!! Specifications


!!! License
* [[http://gadgetforge.gadgetfactory.net/gf/download/frsrelease/142/460/BPC3003_Papilio_One_v2.04.zip|All design files are available under a Completely Open Source Creative Commons Attribution Non-Commercial.]]
to:
>><<

Changed lines 133-138 from:
!! Additional information:
!!!Diagram
>>lrindent round frame bgcolor=#ffffff<<
%center%http:
//www.gadgetfactory.net/images/pap1diag.png
>><<
to:
!!Quick Links
[[http
://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|Xilinx Spartan-3E datasheet]]

[[http://gadgetforge.gadgetfactory.net/gf/download/frsrelease/134/412/BPC3003_2.03%2B.ucf|Xilinx UFC file]]

[[http://www.gadgetfactory.net/blog/wp-content/uploads/2011/02/Papilio_Pins.
png|Pin mapping]]

[[http://gadgetforge.gadgetfactory.net/gf/download/docmanfileversion/8/455/Butterfly_One_Schematic.pdf|Schematic]]

[[http://gadgetforge.gadgetfactory.net/gf/download/frsrelease/142/460/BPC3003_Papilio_One_v2.04.zip|EAGLE files (License CC-BY-SA-NC)]]

!! Specifications


!!! License
* [[http://gadgetforge.gadgetfactory.net/gf/download/frsrelease/142/460/BPC3003_Papilio_One_v2.04.zip|All design files are available under a Completely Open Source Creative Commons Attribution Non-Commercial.]]
May 10, 2013, at 09:46 AM by Jack Gassett -
Changed lines 1-2 from:
(:title Papilio Hardware:)
to:
(:title Papilio One Hardware:)
Changed lines 8-13 from:
!! Papilio One Overview
>>lrindent round frame text-align=justify
<<
The Papilio is an Open Source FPGA development board based on the
Xilinx Spartan 3E FPGA (
[[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|datasheet]]).
It has 48 I/O lines, dual channel USB, integrated JTAG
programmer, 4 power supplies, and a power connector. It provides everything needed to start learning
[[Digital Electronics]].
to:
>>lrindent round frame float:right width:400px<<
'''Contents'''
[[<<]]
[[#Overview|Overview]][[<<]]
[[#Section1|Section Name]][[<<]]
[[#Section2|Section Name]][[<<]]
[[#Section3|Section Name]][[<<]]
[[#Section4|Section Name]][[<<]]
[[#Section5|Section Name]][[<<]]
[[#Section6|Section Name]][[<<]]
[[#Section7|Section Name]][[<<]]
[[#Section8|Section Name]][[<<]]
[[#Section9|Section Name]][[<<]]
[[#Section10|Section Name]]
[[<<]]
[[#Links|Links]][[<<]]
[[#License|License]][[<<]]
[[#Images|Images]][[<<]]
Changed lines 28-29 from:
>>lrindent round frame bgcolor=#ffffff<<
%center%http://papilio.cc/uploads/Papilio/p1sparkfun.jpg
to:
[[#Overview]]
!!Papilio One
>>round frame
<<
The Papilio is an Open Source FPGA development board based on the
Xilinx Spartan 3E FPGA ([[http:
//www.xilinx.com/support/documentation/data_sheets/ds312.pdf|datasheet]]).
It has 48 I/O lines, dual channel USB, integrated JTAG
programmer, 4 power supplies, and a power connector. It provides everything needed to start learning [[Digital Electronics]].
Changed lines 37-48 from:
!!Quick Links
[[http
://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|Xilinx Spartan-3E datasheet]]

[[http://gadgetforge.gadgetfactory.net/gf/download/frsrelease/134/412/BPC3003_2.03%2B.ucf|Xilinx UFC file]]

[[http://www.gadgetfactory.net/blog/wp-content/uploads/2011/02/Papilio_Pins.png|Pin mapping]]

[[http://gadgetforge.gadgetfactory.net/gf/download/docmanfileversion/8/455/Butterfly_One_Schematic.pdf|Schematic]]

[[http://gadgetforge.gadgetfactory.net/gf/download/frsrelease/142/460/BPC3003_Papilio_One_v2.04.zip|EAGLE files (License CC-BY-SA-NC)]]

!! Specifications
to:
>>round frame float:left width:400px bgcolor=#ffffff<<
%width=500%
[[http://papilio.cc/uploads/Papilio/p1sparkfun.jpg|http://papilio.cc/uploads/Papilio/p1sparkfun.jpg]]
>><<
[[<<]]

*Features List
Added lines 65-82:
[[<<]]



!!Quick Links
[[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|Xilinx Spartan-3E datasheet]]

[[http://gadgetforge.gadgetfactory.net/gf/download/frsrelease/134/412/BPC3003_2.03%2B.ucf|Xilinx UFC file]]

[[http://www.gadgetfactory.net/blog/wp-content/uploads/2011/02/Papilio_Pins.png|Pin mapping]]

[[http://gadgetforge.gadgetfactory.net/gf/download/docmanfileversion/8/455/Butterfly_One_Schematic.pdf|Schematic]]

[[http://gadgetforge.gadgetfactory.net/gf/download/frsrelease/142/460/BPC3003_Papilio_One_v2.04.zip|EAGLE files (License CC-BY-SA-NC)]]

!! Specifications
May 10, 2013, at 09:40 AM by Jack Gassett -
Added lines 1-123:
(:title Papilio Hardware:)

(:keywords FPGA, Xilinx, Papilio platform, Firefly platform, Wings, FPGA development, electronics, FPGA India, embedded processors, open source hardware, configurable logic:)

(:description Papilio platform is easy to use FPGA development platform for beginners and a powerful modular design environment for professional developers. Download Papiliio project sources, software, design files, support applications, libraries, Papilio Explorer, Papilio Builder IDE:)

(:include HardwareHeader:)
!! Papilio One Overview
>>lrindent round frame text-align=justify<<
The Papilio is an Open Source FPGA development board based on the
Xilinx Spartan 3E FPGA ([[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|datasheet]]).
It has 48 I/O lines, dual channel USB, integrated JTAG
programmer, 4 power supplies, and a power connector. It provides everything needed to start learning [[Digital Electronics]].
>><<

>>lrindent round frame bgcolor=#ffffff<<
%center%http://papilio.cc/uploads/Papilio/p1sparkfun.jpg
>><<

!!Quick Links
[[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|Xilinx Spartan-3E datasheet]]

[[http://gadgetforge.gadgetfactory.net/gf/download/frsrelease/134/412/BPC3003_2.03%2B.ucf|Xilinx UFC file]]

[[http://www.gadgetfactory.net/blog/wp-content/uploads/2011/02/Papilio_Pins.png|Pin mapping]]

[[http://gadgetforge.gadgetfactory.net/gf/download/docmanfileversion/8/455/Butterfly_One_Schematic.pdf|Schematic]]

[[http://gadgetforge.gadgetfactory.net/gf/download/frsrelease/142/460/BPC3003_Papilio_One_v2.04.zip|EAGLE files (License CC-BY-SA-NC)]]

!! Specifications
!!! Power
* Four independent power rails at 5V, 3.3V, 2.5V, and 1.2V.
* Power supplied by a power connector or USB.
* DC Input Jack.
** Input Voltage (recommended): 6.5-15V
!!! USB
* Two channel USB connection for JTAG and serial communications implemented with [[http://www.ftdichip.com/Documents/DataSheets/DS_FT2232D.pdf|FT2232D]].
* EEPROM memory to store configuration settings for [[http://www.ftdichip.com/Documents/DataSheets/DS_FT2232D.pdf|FT2232]] USB chip.
!!! Spartan 3E FPGA
* 32MHz oscillator that can be used by [[Papilio.DigitalClockManager|Xilinx's DCM to generate any required clock speed]].
* VTQFP-100 footprint that supports [[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|Xilinx XC3S100E, XC3S250E, and XC3S500E]] parts.
* I/O can be set to support 1.2V, 2.5V, or 3.3V.
!!! SPI Flash
* 4M SPI Flash for [[design persistence]].
!!! Wings
* 48 bidirectional I/O lines which can be split up as:
** 1x 32 Bit Wing or
** 3x 16 Bit Wings or
** 6x 8 Bit Wings
* .1" spacing for compatibility with bread boards.
!!! Dimensions
* 2.7"x2.7"
!!! License
* [[http://gadgetforge.gadgetfactory.net/gf/download/frsrelease/142/460/BPC3003_Papilio_One_v2.04.zip|All design files are available under a Completely Open Source Creative Commons Attribution Non-Commercial.]]

!!Inputs/Outputs
!!!I/O Blocks
The I/O blocks provides programmable interface between pins and the Spartan-3E internal logic.
*Features:
**Programmable pull-down, pull-up and float resistors (Pull-down by default on unused pins).
**Programmable input delay.
**Optional keeper circuit (keeps last logic level, see spartan-3E datasheet page 18).
** 2 to 16 mA programmable output current drive strength.
**All I/O pins are in high-impedance state during configuration (program loading). Unused pins are pull-down inputs by default with the Xilinx ISE software.
!!!I/O Banks
*The VCCO jumper selects the voltage for all of the I/O lines, the options are 1.2V, 2.5V, and 3.3V. The recommended setting is 3.3V since most peripherals operate at 3.3V.

!! Power
The Papilio One can be powered from the USB connector, an external power supply, or a battery. The PWRSELECT jumper controls whether the USB connector or the Power Jack/PWRIN connectors are active.

!!! Power Selection

When the USB connector is selected up to 500mA of current is supplied to the 1.2V, 2.5V, and 3.3V LD1117 voltage regulators. The 5V power rail is supplied directly by the USB port and the 5V LD1117 power regulator is inactive.

When the power jack or battery is selected the 5V LD1117 voltage regulator supplies up to 800mA of current to the 1.2V, 2.5V, and 3.3V LD1117 voltage regulators. The power jack or battery must provide at least 6V in order to generate the desired 5V output.

!!! RPAR

The JTAG programming pins on the Spartan 3E always operate at 2.5V while the connected JTAG pins of the FT2232D always operate at 3.3V. This difference in voltage can cause the Spartan 3E to send reverse current back on the 2.5V power rail. The RPAR resistor provides a shunt for this reverse current to be dissipated. The Xilinx application notes recommend the use of RPAR in the case that a voltage regulator cannot handle reverse current. The LD1117 datasheet does not indicate that it can handle reverse current so RPAR was included. Testing has shown that the LD1117 seems to handle the reverse current just fine but boards will be populated with RPAR as a safety precaution. The RPAR resistor consumes 25mA of current so if a battery is being used it is recommended to remove the RPAR resistor to help extend battery life. Please understand that the possible effects of removing the RPAR resistor are the 2.5V rail going higher than 2.5V and possibly damaging the 2.5V voltage regulator. There is an interesting discussion about the need for RPAR [[http://newsgroups.derkeiler.com/Archive/Comp/comp.arch.fpga/2008-03/msg00659.html|here]].

!!! Power Jack

* Input: 6-15V DC
* Current: Draws up to 800mA
* Size: 2.1mm
* Polarity: Positive Tip

!! Memory
The on-board SPI Flash provides 4Mbits of space to store a bitstream that is loaded by the FPGA at start-up. Bitstreams are loaded to SPI Flash using the [[Papilio Loader]].

!! Communications
The Papilio One uses a [[http://www.ftdichip.com/Documents/DataSheets/DS_FT2232D.pdf|FTDI 2232D]] USB chip which provides two channels over one USB connection. One of the channels is configured as a simple UART device and shows up as a virtual COM port. The other channel takes advantage of the MPSSE (Multi-Protocol Synchronous Serial Engine) functionality to implement a high speed JTAG channel for programming the [[http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf|Xilinx Spartan 3E]].
!!!Drivers
The first time the Papilio One is plugged into the computer it will be necessary to install the FTDI device drivers. [[http://ftdichip.com/Drivers/D2XX.htm|Drivers can be downloaded from the FTDI website]].

!!!UART
When the Papilio One is plugged into the USB port both channels will be detected and will show up under the Control Panel as a virtual COM port. The second virtual COM port is the UART channel.

!!!JTAG
The Xilinx device is programmed using any application that can support the FT2232D MPSSE JTAG mode. The [[http://gadgetforge.gadgetfactory.net/gf/project/butterflyloader/|Papilio Loader]] is one such application.

!!!JTAG Programming Port
The JTAG programming port is included for use with external JTAG programmers such as the Xilinx JTAG cables. The Xilinx tools such as Impact and the EDK do not support FT2232D based programmers nor does Xilinx provide any method to add support for non-Xilinx programmers. This external port is provided as a means to use the Xilinx tools with the Papilio One. The Xilinx tools can still be used without an Xilinx programmer by generating bitstreams that can be loaded by the Papilio Loader.

TEMPORARY LIMITATION: In order to use the external JTAG port the FT2232D lines that are connected to the JTAG port need to be put into a HIGH-Z state. This has not been tested yet and will probably require a special application.

!!!EEPROM
Custom VID/PID and configuration data can be loaded into the provided EEPROM using the [[http://ftdichip.com/Resources/Utilities.htm#MProg|FTDI MProg]] application.


!! Misc
!!! Oscillator
The Papilio One has a 32Mhz oscillator that can be converted to any speed desired inside the FPGA using a [[Papilio.DigitalClockManager|Digital Clock Manager]]. The Spartan 3E provides 4 Digital Clock Managers.

!!! LED's
The Papilio One has a power LED, a RX LED, and a TX LED. The power led lights up to indicate that power is being supplied to the board while the RX and TX led's show UART traffic.

!! Additional information:
!!!Diagram
>>lrindent round frame bgcolor=#ffffff<<
%center%http://www.gadgetfactory.net/images/pap1diag.png
>><<
  

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