Papilio.PapilioDUOHardwareGuide History

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June 16, 2015, at 11:46 AM by Jack Gassett -
Changed line 41 from:
*64Mbit Macronix MX25L6445 SPI Flash %newwin%([[http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/3F21BAC2E121E17848257639003A3146/$File/MX25L6445E,%203V,%2064Mb,%20v1.8.pdf|Datasheet]])
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*64Mbit Macronix MX25L6445 SPI Flash %newwin%([[http://www.macronix.com/Lists/Datasheet/Attachments/2474/MX25L6445E,%203V,%2064Mb,%20v1.8.pdf|Datasheet]])
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The 64Mbit Macronix %newwin%[[http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/3F21BAC2E121E17848257639003A3146/$File/MX25L6445E,%203V,%2064Mb,%20v1.8.pdf|MX25L6445]] SPI Flash chip is the largest ever included with a Papilio FPGA. It is the largest available in the 8-SOIC footprint, and is included for good reason! The new multi-boot feature of the Spartan 6 means we can put as many FPGA bit files on the SPI Flash as will fit and use a "golden image" to select which one will boot at startup. Spartan 6 LX9 bit files are 333KBytes in size which means that the Papilio DUO can save up to 23 bit files in SPI Flash. Or, we can save and retrieve user data using techniques like the SmallFS filesystem or [[http://www.papilio.cc/index.php?n=Playground.Bootstrap|bootstrap code]] that loads data from SPI Flash to SRAM at startup.
to:
The 64Mbit Macronix %newwin%[[http://www.macronix.com/Lists/Datasheet/Attachments/2474/MX25L6445E,%203V,%2064Mb,%20v1.8.pdf|MX25L6445]] SPI Flash chip is the largest ever included with a Papilio FPGA. It is the largest available in the 8-SOIC footprint, and is included for good reason! The new multi-boot feature of the Spartan 6 means we can put as many FPGA bit files on the SPI Flash as will fit and use a "golden image" to select which one will boot at startup. Spartan 6 LX9 bit files are 333KBytes in size which means that the Papilio DUO can save up to 23 bit files in SPI Flash. Or, we can save and retrieve user data using techniques like the SmallFS filesystem or [[http://www.papilio.cc/index.php?n=Playground.Bootstrap|bootstrap code]] that loads data from SPI Flash to SRAM at startup.
Changed lines 280-281 from:
-->[[https://github.com/GadgetFactory/Papilio-DUO/blob/master/Papilio_DUO_Schematic.pdf?raw=true|Papilio DUO Schematic (PDF)]]
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-->[[http://www.papilio.cc/uploads/Papilio/Papilio_DUO.pdf?raw=true|Papilio DUO Schematic (PDF)]]
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%lframe height=700 width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[https://github.com/GadgetFactory/Papilio-DUO/blob/master/Papilio_DUO_Schematic.pdf?raw=true|Attach:pduo-schematic2.png]]
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%lframe height=700 width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[http://www.papilio.cc/uploads/Papilio/Papilio_DUO.pdf?raw=true|Attach:pduo-schematic2.png]]
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%lframe width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[http://www.papilio.cc/uploads/Papilio/Papilio%20DUO%20pinout.pdf.zip|http://www.papilio.cc/uploads/Papilio/PapilioDUOPinouts.png]]
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%lframe width=500 bgcolor=#c5d7dd border='1px solid #429ae0' newwin% [[http://www.papilio.cc/uploads/Papilio/Papilio%20DUO%20pinout.pdf|http://www.papilio.cc/uploads/Papilio/PapilioDUOPinouts.png]]
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%lframe width=500 bgcolor=#c5d7dd border='1px solid #429ae0' newwin% [[http://www.papilio.cc/uploads/Papilio/Papilio%20DUO%20pinout.pdf?raw=true|http://www.papilio.cc/uploads/Papilio/PapilioDUOPinouts.png]]
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%lframe width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[http://www.papilio.cc/uploads/Papilio/Papilio%20DUO%20pinout.pdf.zip|http://www.papilio.cc/uploads/Papilio/PapilioDUOPinouts.png]]
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!!Papilio DUO
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!!Papilio DUO Hardware Guide
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[[<<]]

%lframe width=500 bgcolor=#c5d7dd border='1px solid #429ae0' newwin% [[http://www.papilio.cc/uploads/Papilio/Papilio%20DUO%20pinout.pdf?raw=true|http://www.papilio.cc/uploads/Papilio/PapilioDUOPinouts.png]]
>>postit<<
%notetitle% Papilio DUO Pinouts%%

Click the image to load a PDF version of Papilio DUO pinouts diagram
>><<
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%lframe height=700 width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[https://github.com/GadgetFactory/Papilio-DUO/blob/master/Papilio_DUO_Schematic.pdf?raw=true|Attach:pduo-schematic.png]]
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%lframe height=700 width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[https://github.com/GadgetFactory/Papilio-DUO/blob/master/Papilio_DUO_Schematic.pdf?raw=true|Attach:pduo-schematic2.png]]
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%lframe height=700 width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[https://github.com/GadgetFactory/Papilio-Pro/blob/master/BPC3010_Papilio_Pro.pdf?raw=truee|Attach:ppro-schematic.png]]
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%lframe height=700 width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[https://github.com/GadgetFactory/Papilio-DUO/blob/master/Papilio_DUO_Schematic.pdf?raw=true|Attach:pduo-schematic.png]]
Deleted lines 312-319:
>><<
[[<<]]

%lframe width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro-assembly.png|Attach:ppro-assembly.png]]
>>postit<<
%notetitle% Assembly View%%

Click the image for a full size view of the boards part layout.
Changed line 278 from:
-->[[http://forum.gadgetfactory.net/index.php?/files/file/235-papilio-duo-generic-ucf/|Papilio Pro Generic User Constraint File (UCF)]]
to:
-->[[http://forum.gadgetfactory.net/index.php?/files/file/235-papilio-duo-generic-ucf/|Papilio DUO Generic User Constraint File (UCF)]]
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%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0' newwin% [[Attach:Papilio pro.png|Attach:Papilio pro.png]]
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0' newwin% [[Attach:papilio pro2.png|Attach:papilio pro2.png]]
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%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0' newwin% [[Attach:PapilioDUO.png|Attach:PapilioDUO.png]]
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0' newwin% [[Attach:papilioduo2.png|Attach:papilioduo2.png]]
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(:include Papilio.PapilioProLinks :)
to:
->'''Papilio DUO Design Files'''
-->[[http
://forum.gadgetfactory.net/index.php?/files/file/235-papilio-duo-generic-ucf/|Papilio Pro Generic User Constraint File (UCF)]]
-->[[https://github.com/GadgetFactory/Papilio-DUO/archive/master.zip|Papilio DUO EAGLE Design Files]]
-->[[https://github.com/GadgetFactory/Papilio-DUO/blob/master/Papilio_DUO_Schematic.pdf?raw=true|Papilio DUO Schematic (PDF)]]

->'''Community Links'''
-->[[http://forum.gadgetfactory.net/index.php?/forum/120-papilio-duo/|Papilio DUO Forum]]
Changed line 252 from:
There is a pullup resistor on the AVR reset line. If the FPGA pin that is connected to the AVR reset line is place in a high-z state then the pullup resistor will cause the AVR reset line to be high and the AVR will run. When the FPGA is in a reset state all pins are in high-z so one way to force the AVR to run is to hold down the FPGA reset line.
to:
There is a physical 10K pullup resistor connected to the AVR reset line. If the FPGA pin that is connected to the AVR reset line is placed in a high-z state then the pullup resistor will cause the AVR reset line to be high and the AVR will run. When the FPGA is in a reset state all pins are in high-z so one way to force the AVR to run is to hold down the FPGA reset line.
Changed lines 215-219 from:
->If you want to use the Xilinx tools such as EDK, Chipscope, or Impact with the Papilio you need a way to use a Xilinx programming cable. The Papilio has a Xilinx JTAG header but the problem is that in the default mode the FT2232D USB chip is connected to the JTAG pins and interferes with programming. What is needed is to put the FT2232 into a mode where the JTAG pins go into High-Z leaving the Xilinx JTAG pins free for the programming cable. To learn more about using a Xilinx Programming Cable visit the [[http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/xilinx-programming-cable-with-papilio-r39|original forum post]] or [[http://www.gadgetfactory.net/2012/09/use-a-xilinx-programming-cable-with-the-papilio/|blog post]].
to:
->If you want to use the Xilinx tools such as EDK, Chipscope, or Impact with the Papilio you need a way to use a Xilinx programming cable. The Papilio has a Xilinx JTAG header but the problem is that in the default mode the FT2232H USB chip is connected to the JTAG pins and interferes with programming. What is needed is to put the FT2232 into a mode where the JTAG pins go into High-Z leaving the Xilinx JTAG pins free for the programming cable. To learn more about using a Xilinx Programming Cable visit the [[http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/xilinx-programming-cable-with-papilio-r39|original forum post]] or [[http://www.gadgetfactory.net/2012/09/use-a-xilinx-programming-cable-with-the-papilio/|blog post]].

>>tip<<
An external programmer may not be necessary to use the Xilinx tools. The Papilio DUO may be detected by the Digilent cable plugin which will allow it to be used with the Xilinx tools. This is an unsupported feature that may or may not work. We recommend using the Papilio tools to load bit files to the Papilio, but if you need to use the Papilio with the EDK or Chipscope software then check to see if the Digilent plugin detects your board. If not then we recommend using the JTAG port with an external programmer.
>><<
Changed line 175 from:
Please note that 5V tolerance means that you can connect 5V logic to these pins but the pins are not driven at 5V. The pins provide 3.3V which is high enough to trigger a "High" state for 5V logic levels. A few boards, such as RAMPS, need a 5V logic level to work correctly. Unfortunately 5V tolerance will not work with these rare cases.
to:
Please note that 5V tolerance means that you can connect 5V logic to these pins but the pins are not driven at 5V. The pins provide 3.3V which is high enough to trigger a "High" state for 5V logic levels. A few boards, such as RAMPS, need a full 5 Volts to work correctly. Unfortunately 5V tolerance will not work with these rare cases.
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||RESET||Input||FPGA Reset||N/A||N/A||P37||
to:
||FPGA RESET||Input||FPGA Reset||N/A||N/A||P37||
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||RESET||Input||AVR Reset||N/A||N/A||P139||
to:
||AVR RESET||Input||AVR Reset||N/A||N/A||P139||
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%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:avrreset-callout.png
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%lframe width=200 bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:avrreset-callout.png
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%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:reset-callout.png
%rframe width=300px% [[Attach:reset-schematic.png|Attach:reset-schematic.png]]
Pressing the reset button will cause the Spartan 6 FPGA to do a hard reset and reload the first bit file from SPI Flash. This is a pretty drastic measure that will wipe out anything running on the FPGA. In most cases it is more desirable to utilize a user button to perform a reset within your design that just initializes all registers to zero.
to:
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:avrreset-callout.png
%rframe width=300px% [[Attach:avrreset-schematic.png|Attach:avrreset-schematic.png]]
The AVR reset pin is connected to and under control of the FPGA (Pin139) so the running state of the AVR is dependent on the circuit you have loaded to the FPGA. The default configuration is to connect the AVR reset pin to the user switch (SW1) and invert it so that the AVR is running when SW1 is up and stopped when SW1 is down. But please note, not all FPGA circuits are setup that way, you will need to look at the schematic for the circuit you have loaded. For example, the default circuit that is loaded to the Papilio DUO when it ships directly connects the AVR reset to a pullup resistor so it is constantly running - the user switch has no effect.

The AVR reset is active low which means that the AVR is in a reset state when the reset line is low.

There is a pullup resistor on the AVR reset line. If the FPGA pin that is connected to the AVR reset line is place in a high-z state then the pullup resistor will cause the AVR reset line to be high and the AVR will run. When the FPGA is in a reset state all pins are in high-z so one way to force the AVR to run is to hold down the FPGA reset line.

The AVR reset line is also connected to the RST pin of the Arduino Mega Header. This is the pin that is next to IOREF and 3.3V, near the Analog pins. If your FPGA circuit directly drives the AVR reset pin then it is a bad idea to also drive from this connection. If you want to use the RST header pin then you will need to place a pullup or pulldown resistor in your FPGA circuit on the reset pin (P139).
Changed line 254 from:
||RESET||Input||FPGA Reset||N/A||N/A||P37||
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||RESET||Input||AVR Reset||N/A||N/A||P139||
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%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:reset-callout.png
%rframe width=300px% [[Attach:reset-schematic.png|Attach:reset-schematic.png]]
to:
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:duoreset-callout.png
%rframe width=300px% [[Attach:duoreset-schematic.png|Attach:duoreset-schematic.png]]
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%rframe height=100px% [[Attach:duoled-schematic.png|Attach:duoled-schematic.png]]
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%rframe height=100px% [[Attach:duoled-schematic2.png|Attach:duoled-schematic2.png]]
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%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:led-callout.png
%rframe height=100px% [[Attach:led-schematic.png|Attach:led-schematic.png]]
The Papilio DUO provides one user LED that is connected directly to the Spartan 6 FPGA. It is not shared with any of the I/O pins and can be controlled directly from your VHDL or sketches.
to:
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:duoled-callout.png
%rframe height=100px% [[Attach:duoled-schematic.png|Attach:duoled-schematic.png]]
The Papilio DUO provides one user LED that is connected to pin 13, just like with the Arduino. The LED can be controlled by accessing pin 13 in your sketches or directly from the FPGA pin in your circuits.
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||LED1||Output||USER LED1||N/A||N/A||P112||
to:
||LED||Output||USER LED||13||N/A||P134||
Changed lines 273-274 from:
%center%[[http://creativecommons.org/licenses/by-nc-sa/3.0/|http://i.creativecommons.org/l/by-nc-sa/3.0/88x31.png]]
Papilio DUO is licensed under a [[http://creativecommons.org/licenses/by-nc-sa/3.0/|Creative Commons Attribution-ShareAlike 3.0 Unported License]].
to:
%center%[[http://creativecommons.org/licenses/by-sa/4.0/|https://i.creativecommons.org/l/by-sa/4.0/88x31.png]]
Papilio DUO is licensed under a [[http://creativecommons.org/licenses/by-sa/4.0/|Creative Commons Attribution-ShareAlike 4.0 International License]].
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Papilio DUO copyright Jack Gassett, Gadget Factory.
to:
Papilio DUO copyright 2014 Jack Gassett, Gadget Factory.
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->The Papilio One (Spartan 3E) offered 4 Digital Clock Managers (DCM) but did not offer any Phase-Locked Loops (PLL). The Papilio Pro (Spartan 6) offers the more flexible CMT which provides both DCM's and PLL's!
to:
->The Papilio One (Spartan 3E) offered 4 Digital Clock Managers (DCM) but did not offer any Phase-Locked Loops (PLL). The Papilio DUO (Spartan 6) offers the more flexible CMT which provides both DCM's and PLL's!
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->The Papilio Pro (Spartan 6) has direct TMDS I/O support which means that DVI and HDMI interfaces can be implemented without any extra chips.
to:
->The Papilio DUO (Spartan 6) has direct TMDS I/O support which means that DVI and HDMI interfaces can be implemented without any extra chips.
Changed line 112 from:
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio Pro Pin||
to:
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio DUO Pin||
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The 64Mbit Macronix %newwin%[[http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/3F21BAC2E121E17848257639003A3146/$File/MX25L6445E,%203V,%2064Mb,%20v1.8.pdf|MX25L6445]] SPI Flash chip is the largest ever included with a Papilio FPGA. It is the largest available in the 8-SOIC footprint, and is included for good reason! The new multi-boot feature of the Spartan 6 means we can put as many FPGA bit files on the SPI Flash as will fit and use a "golden image" to select which one will boot at startup. Spartan 6 LX9 bit files are 333KBytes in size which means that the Papilio Pro can save up to 23 bit files in SPI Flash. Or, we can save and retrieve user data using techniques like the SmallFS filesystem or [[http://www.papilio.cc/index.php?n=Playground.Bootstrap|bootstrap code]] that loads data from SPI Flash to SRAM at startup.
to:
The 64Mbit Macronix %newwin%[[http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/3F21BAC2E121E17848257639003A3146/$File/MX25L6445E,%203V,%2064Mb,%20v1.8.pdf|MX25L6445]] SPI Flash chip is the largest ever included with a Papilio FPGA. It is the largest available in the 8-SOIC footprint, and is included for good reason! The new multi-boot feature of the Spartan 6 means we can put as many FPGA bit files on the SPI Flash as will fit and use a "golden image" to select which one will boot at startup. Spartan 6 LX9 bit files are 333KBytes in size which means that the Papilio DUO can save up to 23 bit files in SPI Flash. Or, we can save and retrieve user data using techniques like the SmallFS filesystem or [[http://www.papilio.cc/index.php?n=Playground.Bootstrap|bootstrap code]] that loads data from SPI Flash to SRAM at startup.
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||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio Pro Pin||
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||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio DUO Pin||
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The Papilio Pro has a 32Mhz oscillator that can be converted to any speed desired inside the FPGA using the Clock Management Tile (CMT). There are two PLLs and two [[http://www.papilio.cc/index.php?n=Papilio.DigitalClockManager|Digital Clock Managers (DCM)]] available for your designs.
to:
The Papilio DUO has a 32Mhz oscillator that can be converted to any speed desired inside the FPGA using the Clock Management Tile (CMT). There are two PLLs and two [[http://www.papilio.cc/index.php?n=Papilio.DigitalClockManager|Digital Clock Managers (DCM)]] available for your designs.
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||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio Pro Pin||
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||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio DUO Pin||
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The JTAG header on the Papilio Pro is provided for a couple different reasons:
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The JTAG header on the Papilio DUO is provided for use with external programmers:
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'''Bypass the FPGA and use the FT2232 as a JTAG/SPI/MPSSE Programmer'''
->The Papilio Pro provides the JP4 pin header, jumping this header will hold the Spartan 6 FPGA in a reset state which frees up the JTAG pins to be controlled by the FT2232. OpenOCD, FlashRAM, and any other FT2232 based software should work directly with this method.
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||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio Pro Pin||
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||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio DUO Pin||
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||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio Pro Pin||
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||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio DUO Pin||
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||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio Pro Pin||
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||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio DUO Pin||
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The Papilio Pro provides one user LED that is connected directly to the Spartan 6 FPGA. It is not shared with any of the I/O pins and can be controlled directly from your VHDL or sketches.
to:
The Papilio DUO provides one user LED that is connected directly to the Spartan 6 FPGA. It is not shared with any of the I/O pins and can be controlled directly from your VHDL or sketches.
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||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio Pro Pin||
to:
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio DUO Pin||
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Papilio Pro is licensed under a [[http://creativecommons.org/licenses/by-nc-sa/3.0/|Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License]].
to:
Papilio DUO is licensed under a [[http://creativecommons.org/licenses/by-nc-sa/3.0/|Creative Commons Attribution-ShareAlike 3.0 Unported License]].
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Papilio Pro copyright Jack Gassett, Gadget Factory.
to:
Papilio DUO copyright Jack Gassett, Gadget Factory.
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%notetitle% Papilio Pro%%

Click the images for full size hi-resolution views of the Papilio Pro.
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%notetitle% Papilio DUO%%

Click the images for full size hi-resolution views of the Papilio DUO.
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%notetitle% Papilio Pro Schematic%%

Click the image to load a PDF version of the Papilio Pro Schematic
to:
%notetitle% Papilio DUO Schematic%%

Click the image to load a PDF version of the Papilio DUO Schematic
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One of the big improvements with the Papilio DUO is its power supply. The Spartan 6 simplifies the power requirements which allowed us to use a high efficiency %newwin%[[http://cds.linear.com/docs/Datasheet/3419fa.pdf|LTC3419]] switching power supply at about the same component cost as the Papilio One's power supply. The linear regulators used in the Papilio One would noticeably heat up when a complicated, high speed design, like the ZPUino, was running. With the Papilio DUO there is no detectable heat generated, even when the most demanding designs are running!
to:
One of the strengths of the Papilio DUO is its power supply. The Spartan 6 simplifies the power requirements which allowed us to use a high efficiency %newwin%[[http://cds.linear.com/docs/Datasheet/3419fa.pdf|LTC3419]] switching power supply at about the same component cost as the Papilio One's power supply. The linear regulators used in the Papilio One would noticeably heat up when a complicated, high speed design, like the ZPUino, was running. With the Papilio DUO there is no detectable heat generated, even when the most demanding designs are running!
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%lframe width=200 bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:switch-callout.png
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%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:switch-callout.png
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'''Arduino Leonardo Compatibility'''
While the ATmega32U4 design is derived from the Arduino Leonardo design it was necessary to re-order the location of the pins to achieve routing of the design on a single layer. This means that the ISP, PWM, and I2C pins are not in the same location as they are on the Leonardo. In the case of the SPI pins they are located in the same location as the Arduino UNO which is actually more convenient. The different pin locations is handled by a pin mapping in the DesignLab IDE which makes everything work just the same as the Arduino Leonardo does. As long as you use the DesignLab IDE and select the Papilio DUO - AVR board type the pin locations will be mapped correctly. Using the Arduino Leonardo board type will not give the expected results since the pins will be in the wrong locations. It is possible to take the Papilio DUO variant from the DesignLab IDE and add it to the Arduino IDE, we will try to provide a package for this in the future.
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Deleted lines 176-178:

'''Arduino Leonardo Compatibility'''
While the ATmega32U4 design is derived from the Arduino Leonardo design it was necessary to re-order the location of the pins to achieve routing of the design on a single layer. This means that the ISP, PWM, and I2C pins are not in the same location as they are on the Leonardo. In the case of the SPI pins they are located in the same location as the Arduino UNO which is actually more convenient. The different pin locations is handled by a pin mapping in the DesignLab IDE which makes everything work just the same as the Arduino Leonardo does. As long as you use the DesignLab IDE and select the Papilio DUO - AVR board type the pin locations will be mapped correctly. Using the Arduino Leonardo board type will not give the expected results since the pins will be in the wrong locations. It is possible to take the Papilio DUO variant from the DesignLab IDE and add it to the Arduino IDE, we will try to provide a package for this in the future.
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%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:switch-callout.png
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%lframe width=200 bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:switch-callout.png
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>><<
[[<<]]
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[[#PProSwitch|User Switch]][[<<]]
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%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:osc-callout.png
%rframe width=300px% [[Attach:osc-schematic.png|Attach:osc-schematic.png]]
The Papilio Pro has a 32Mhz oscillator that can be converted to any speed desired inside the FPGA using the Clock Management Tile (CMT). There are two PLLs and two [[http://www.papilio.cc/index.php?n=Papilio.DigitalClockManager|Digital Clock Managers (DCM)]] available for your designs.
to:
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:switch-callout.png
%rframe width=300px% [[Attach:switch-schematic.png|Attach:switch-schematic.png]]
The Papilio DUO has a user switch (SW1) that can be used for any purpose required. By default most Papilio DUO circuits have the switch setup to enable or disable the AVR.

>>warning<<
If your circuit implements the default AVR reset then putting SW1 to the up position turns the AVR on, while putting it in the down position turns it off
. Please be do not be confused if the switch does not work this way. It only works if the circuit you have loaded sets up the switch to work this way. For example, the circuit that is loaded to the Papilio DUO from the factory is not setup to work this way. Instead it hard wires the AVR to always be on.
>><<
Deleted lines 202-206:
|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio Pro Pin||
||CLK||Input||External 32Mhz Oscillator||N/A||N/A||P94||
\\
Changed line 228 from:
!!!Reset
to:
!!!FPGA Reset
Added lines 238-248:
----
[[#PProAVRReset]]
!!!AVR Reset
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:reset-callout.png
%rframe width=300px% [[Attach:reset-schematic.png|Attach:reset-schematic.png]]
Pressing the reset button will cause the Spartan 6 FPGA to do a hard reset and reload the first bit file from SPI Flash. This is a pretty drastic measure that will wipe out anything running on the FPGA. In most cases it is more desirable to utilize a user button to perform a reset within your design that just initializes all registers to zero.
[[<<]]
|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio Pro Pin||
||RESET||Input||FPGA Reset||N/A||N/A||P37||
\\
Changed line 9 from:
[[#PProAVR|ATmega32U4 Microcontroller]][[<<]]
to:
[[#PProAVR|AVR ATmega32U4]][[<<]]
Changed line 83 from:
The Papilio Pro has a 32Mhz oscillator that can be converted to any speed desired inside the FPGA using the Clock Management Tile (CMT). There are two PLLs and two [[http://www.papilio.cc/index.php?n=Papilio.DigitalClockManager|Digital Clock Managers (DCM)]] available for your designs.
to:
The ATmega32U4 chip is a unique addition that gives full Arduino compatibility to the Papilio DUO. It is derived from the Arduino Leonardo design.
Deleted lines 84-89:

|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio Pro Pin||
||CLK||Input||External 32Mhz Oscillator||N/A||N/A||P94||
\\
Changed line 81 from:
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:avr-callout.png
to:
%lframe width=200 bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:avr-callout.png
Added line 9:
[[#PProAVR|ATmega32U4 Microcontroller]][[<<]]
Changed lines 80-81 from:
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:osc-callout.png
%rframe width=300px% [[Attach:osc-schematic.png|Attach:osc-schematic.png]]
to:
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:avr-callout.png
%rframe width=300px% [[Attach:avr-schematic.png|Attach:avr-schematic.png]]
Changed line 129 from:
The pinout of the SRAM is too many pins to list here, please refer to the ucf file for a full pinout.
to:
The ZPUino Soft Processor integrates the SRAM which gives your ZPUino sketches 512KB or 2MByte of code space!
Deleted lines 131-135:

>>tip<<
The ZPUino Soft Processor integrates the SRAM which gives your ZPUino sketches 512KB or 2MByte of code space!
>><<
[[<<]]
Changed lines 159-160 from:
Analog pins 2-5 on the ATmega32U4 are dual purpose pins. They are both Analog pins and the JTAG programming pins.
to:
Analog pins 2-5 on the ATmega32U4 are shared with the FPGA because they are dual purpose pins, both analog and JTAG. A2-5 are connected to Pins 28, 30, 32, and 34 which allows the FPGA to act as a debugger for the ATmega32U4.

'''Analog Pins'''
There are six analog pins on the Papilio DUO. Since an FPGA does not natively support Analog input we are using the ATmega32U4 to implement the analog pins. The Analog pins must be read from the ATmega32U4, if their output is needed on the FPGA then we recommend using the AVR to Wishbone bridge to transfer their value. Or alternatively, read their value with the ATmega32U4 and place the result on the shared pins 0-7 to be read by the FPGA.

'''FPGA Only Pins'''
Pins 17-53 are connected exclusively to the FPGA and are 3.3V without 5V tolerance. The exception is pins 28, 30, 32, and 34 which are also connected to the JTAG pins of the ATmega32U4 in order to allow step by step debugging.

'''ATmega32U4 JTAG Pins'''
The ATmega32U4 JTAG pin fuses are enabled by default so that JTAG debugging is enabled at power on. In order to prevent the JTAG pins, which are shared with FPGA pins, from interfering with normal operation the JTAG registers are set to disable the JTAG pins when a sketch is loaded.
Deleted lines 177-182:
'''FPGA Only Pins'''
Pins 17-53 are connected exclusively to the FPGA and are 3.3V without 5V tolerance. The exception is pins 28, 30, 32, and 34 which are also connected to the JTAG pins of the ATmega32U4 in order to allow step by step debugging. Please note that the JTAG pins are also A2-A5 so the corresponding FPGA pins are also connected to A2-5.

'''ATmega32U4 JTAG Pins'''
The ATmega32U4 JTAG pin fuses are enabled by default so that JTAG debugging is enabled at power on. In order to prevent the JTAG pins, which are shared with FPGA pins, from interfering with normal operation the JTAG registers are set to disable the JTAG pins when a sketch is loaded.
Deleted lines 179-181:

'''Analog Pins'''
There are six analog pins on the Papilio DUO. Since an FPGA does not natively support Analog input we are using the ATmega32U4 to implement the analog pins. The Analog pins must be read from the ATmega32U4, if their output is needed on the FPGA then we recommend using the AVR to Wishbone bridge to transfer their value. Or alternatively, read their value with the ATmega32U4 and place the result on the shared pins 0-7 to be read by the FPGA.
Changed line 160 from:
''''Shared Pins''''
to:
'''Shared Pins - Digital IO'''
Changed lines 163-166 from:
''''5V Tolerance''''
to:
'''Shared Pins - Analog'''
Analog pins 2-5 on the ATmega32U4 are dual purpose pins. They are both Analog pins and the JTAG programming pins.

'''5V Tolerance
'''
Changed lines 175-181 from:
''''Arduino Leonardo Compatibility''''
to:
'''FPGA Only Pins'''
Pins 17-53 are connected exclusively to the FPGA and are 3.3V without 5V tolerance. The exception is pins 28, 30, 32, and 34 which are also connected to the JTAG pins of the ATmega32U4 in order to allow step by step debugging. Please note that the JTAG pins are also A2-A5 so the corresponding FPGA pins are also connected to A2-5.

'''ATmega32U4 JTAG Pins'''
The ATmega32U4 JTAG pin fuses are enabled by default so that JTAG debugging is enabled at power on. In order to prevent the JTAG pins, which are shared with FPGA pins, from interfering with normal operation the JTAG registers are set to disable the JTAG pins when a sketch is loaded.

'''Arduino Leonardo Compatibility
'''
Changed line 184 from:
''''Analog Pins''''
to:
'''Analog Pins'''
Deleted lines 185-188:

The I/O of the Papilio Pro is backwards compatible with the Papilio One, all existing Papilio Wings and MegaWings work with the Papilio Pro.

The major difference between the Papilio Pro and Papilio One with respect to User I/O is the available voltage levels. The Papilio Pro sets all I/O voltage pins to 3.3V while the Papilio One can switch between 1.2V, 2.5V, and 3.3V. This was a seldom used feature that was dropped in the Papilio Pro for greater compatibility. Additionally, the Papilio Pro does not provide a 2.5V power rail, the 2.5V pin on the Wing Header is left unconnected. There are no Wings or MegaWings that use 2.5V power and there probably never will be... 3.3V seems to be the defacto standard for current peripherals.
Changed line 156 from:
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:duoio-callout.png
to:
%lframe width=200 bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:duoio-callout2.png
Added line 76:
Changed lines 78-83 from:
[[#PProPower]]
!!!Power
%lframe width=200px bgcolor=#c5d7dd border='1px solid
#429ae0'% Attach:duopower-callout.png
%rframe text-align
=center height=220px% [[Attach:duopower-schematic.png|Attach:duopower-schematic.png]]|'''Power Schematic'''

One of the big improvements with the Papilio DUO is its power supply. The Spartan 6 simplifies
the power requirements which allowed us to use a high efficiency %newwin%[[http://cds.linear.com/docs/Datasheet/3419fa.pdf|LTC3419]] switching power supply at about the same component cost as the Papilio One's power supply. The linear regulators used in the Papilio One would noticeably heat up when a complicated, high speed design, like the ZPUino, was running. With the Papilio DUO there is no detectable heat generated, even when the most demanding designs are running!
to:
[[#PProAVR]]
!!!ATmega32U4 "Arduino Leonardo" compatible Microcontroller
%lframe bgcolor=
#c5d7dd border='1px solid #429ae0'% Attach:osc-callout.png
%rframe width=300px% [[Attach:osc-schematic.png|Attach:osc-schematic.png]]
The Papilio Pro has a 32Mhz oscillator that can be converted to any speed desired inside the FPGA using
the Clock Management Tile (CMT). There are two PLLs and two [[http://www.papilio.cc/index.php?n=Papilio.DigitalClockManager|Digital Clock Managers (DCM)]] available for your designs.
Added lines 84-89:

|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio Pro Pin||
||CLK||Input||External 32Mhz Oscillator||N/A||N/A||P94||
\\
Added lines 91-98:
[[#PProPower]]
!!!Power
%lframe width=200px bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:duopower-callout.png
%rframe text-align=center height=220px% [[Attach:duopower-schematic.png|Attach:duopower-schematic.png]]|'''Power Schematic'''

One of the big improvements with the Papilio DUO is its power supply. The Spartan 6 simplifies the power requirements which allowed us to use a high efficiency %newwin%[[http://cds.linear.com/docs/Datasheet/3419fa.pdf|LTC3419]] switching power supply at about the same component cost as the Papilio One's power supply. The linear regulators used in the Papilio One would noticeably heat up when a complicated, high speed design, like the ZPUino, was running. With the Papilio DUO there is no detectable heat generated, even when the most demanding designs are running!
[[<<]]
----
Added lines 160-162:
''''Shared Pins''''
Pins 0-16 are connected to both the ATmega32U4 and the Spartan 6 FPGA. These pins can be used to transfer data between the two chips, provide digital logic to the AVR chip, connect a Logic Analyzer to the AVR chip, or transfer Analog data to the FPGA; to name a few uses. The AVR is set to run at 3.3V so there is no voltage mismatch between the AVR and FPGA. 5V tolerance for shields is implemented as described below.
Added lines 172-174:
''''Arduino Leonardo Compatibility''''
While the ATmega32U4 design is derived from the Arduino Leonardo design it was necessary to re-order the location of the pins to achieve routing of the design on a single layer. This means that the ISP, PWM, and I2C pins are not in the same location as they are on the Leonardo. In the case of the SPI pins they are located in the same location as the Arduino UNO which is actually more convenient. The different pin locations is handled by a pin mapping in the DesignLab IDE which makes everything work just the same as the Arduino Leonardo does. As long as you use the DesignLab IDE and select the Papilio DUO - AVR board type the pin locations will be mapped correctly. Using the Arduino Leonardo board type will not give the expected results since the pins will be in the wrong locations. It is possible to take the Papilio DUO variant from the DesignLab IDE and add it to the Arduino IDE, we will try to provide a package for this in the future.
Changed lines 176-177 from:
to:
There are six analog pins on the Papilio DUO. Since an FPGA does not natively support Analog input we are using the ATmega32U4 to implement the analog pins. The Analog pins must be read from the ATmega32U4, if their output is needed on the FPGA then we recommend using the AVR to Wishbone bridge to transfer their value. Or alternatively, read their value with the ATmega32U4 and place the result on the shared pins 0-7 to be read by the FPGA.
Added lines 186-198:
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:osc-callout.png
%rframe width=300px% [[Attach:osc-schematic.png|Attach:osc-schematic.png]]
The Papilio Pro has a 32Mhz oscillator that can be converted to any speed desired inside the FPGA using the Clock Management Tile (CMT). There are two PLLs and two [[http://www.papilio.cc/index.php?n=Papilio.DigitalClockManager|Digital Clock Managers (DCM)]] available for your designs.
[[<<]]

|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio Pro Pin||
||CLK||Input||External 32Mhz Oscillator||N/A||N/A||P94||
\\

----
[[#PProSwitch]]
!!!User Switch
Changed lines 142-143 from:
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:io-callout.png
%rframe height=250px% [[Attach:io-schematic.png|Attach:io-schematic.png]]
to:
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:duoio-callout.png
%rframe height=250px% [[Attach:duoio-schematic.png|Attach:duoio-schematic.png]]
The Papilio DUO is unique in that it is the first Papilio board to adopt the Arduino Mega form factor. The Arduino form factor gives us 54 I/O pins and 6 Analog pins.

''''5V Tolerance''''
The first 14 pins, those that comprise the shortened Arduino Uno footprint, are 5V tolerant. This means that you can safely attach any of your 5V Arduino shields without damaging the 3.3V pins of the FPGA.

5V tolerance is accomplished by placing series current limiting resistors in line with the FPGA pins. This is a common and widely accepted practice with Xilinx FPGA's and has been tested extensively. These resistors protect from too much current being applied to the FPGA pins and the internal clamp diodes on the pins convert the extra voltage into reverse current. So as long as our power supply can safely handle reverse current, which it can, we achieve 5V tolerance. For those interested in learning more there is an [[http://newsgroups.derkeiler.com/Archive/Comp/comp.arch.fpga/2008-03/msg00659.html|interesting discussion here]].

>>tip<<
Please note that 5V tolerance means that you can connect 5V logic to these pins but the pins are not driven at 5V. The pins provide 3.3V which is high enough to trigger a "High" state for 5V logic levels. A few boards, such as RAMPS, need a 5V logic level to work correctly. Unfortunately 5V tolerance will not work with these rare cases.
>><<

''''Analog Pins''''
Changed line 11 from:
[[#PProSdram|SDRAM]][[<<]]
to:
[[#PProSdram|SRAM]][[<<]]
Changed line 107 from:
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:sram-callout.png
to:
%lframe width=200px bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:sram-callout.png
Changed lines 109-110 from:
The Papilio DUO includes a 64Mbit Micron %newwin%[[http://download.micron.com/pdf/datasheets/dram/sdram/64MSDRAM.pdf|MT48LC4M16]] SDRAM chip. This additional SDRAM will open up a whole new breed of FPGA applications for the Papilio. The timing requirements and refresh signals of the SDRAM chip do make interfacing it more of a challenge than interfacing regular SRAM, or the internal BRAM. We are working on a SDRAM controller that you can drop into your designs so the SDRAM can be used like regular SRAM.
to:
The Papilio DUO includes a 512KB ISSI %newwin%[[http://www.issi.com/WW/pdf/61-64WV5128Axx-Bxx.pdf|IS61WV5128BLL]] or 2MB ISSI %newwin%[[http://www.issi.com/WW/pdf/61-64WV20488.pdf|IS61WV20488BLL]] SRAM chip. SRAM is much, much easier to use with FPGA projects since there are no special timing requirements to follow. While we don't get as much SRAM memory space as we would for the same priced SDRAM or DDR memory chip, the trade off in ease of use more then makes up for it.
Deleted lines 111-116:

!!!SDRAM Designs
*[[http://hamsterworks.co.nz/mediawiki/index.php/SDRAM_Memory_Controller|Hamster's SDRAM Controller]]
*[[https://github.com/alvieboy/ZPUino-HDL/blob/dcache/zpu/hdl/zpuino/boards/papilio-pro/S6LX9/sdram_hamster.vhd|Alvie's ZPUino SDRAM controller.]] (derived from Hamster's SDRAM controller).
*[[https://github.com/alvieboy/ZPUino-HDL/blob/dcache/zpu/hdl/zpuino/boards/papilio-pro/S6LX9/sdram_wrap.vhd|Wishbone wrapper for Alvie's SDRAM controller.]]
*[[http://www.xilinx.com/support/documentation/application_notes/xapp394.pdf|XAPP 394 Interfacing Mobile SDRAM with CPLD's.]]
Changed lines 115-120 from:
The ZPUino Soft Processor includes a SDRAM controller which gives your ZPUino sketches 8MByte of code space!
to:
The pinout of the SRAM is too many pins to list here, please refer to the ucf file for a full pinout.
>><<
[[<<]]

>>tip<<
The ZPUino Soft Processor integrates the SRAM which gives your ZPUino sketches 512KB or 2MByte
of code space!
Changed line 94 from:
%cframe text-align=center width=500% [[Attach:duousb-schematic.png|Attach:duusb-schematic.png]]|'''USB Schematic'''
to:
%cframe text-align=center width=500% [[Attach:duousb-schematic.png|Attach:duousb-schematic.png]]|'''USB Schematic'''
Changed lines 106-109 from:
!!!SDRAM
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:sdram-callout.png
%rframe height=300px% [[Attach:sdram-schematic.png|Attach:sdram-schematic.png]]
The Papilio Pro includes a 64Mbit Micron %newwin%[[http://download.micron.com/pdf/datasheets/dram/sdram/64MSDRAM.pdf|MT48LC4M16]] SDRAM chip. This additional SDRAM will open up a whole new breed of FPGA applications for the Papilio. The timing requirements and refresh signals of the SDRAM chip do make interfacing it more of a challenge than interfacing regular SRAM, or the internal BRAM. We are working on a SDRAM controller that you can drop into your designs so the SDRAM can be used like regular SRAM.
to:
!!!SRAM
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:sram-callout.png
%rframe height=300px% [[Attach:sram-schematic.png|Attach:sram-schematic.png]]
The Papilio DUO includes a 64Mbit Micron %newwin%[[http://download.micron.com/pdf/datasheets/dram/sdram/64MSDRAM.pdf|MT48LC4M16]] SDRAM chip. This additional SDRAM will open up a whole new breed of FPGA applications for the Papilio. The timing requirements and refresh signals of the SDRAM chip do make interfacing it more of a challenge than interfacing regular SRAM, or the internal BRAM. We are working on a SDRAM controller that you can drop into your designs so the SDRAM can be used like regular SRAM.
Changed line 94 from:
%cframe text-align=center width=500% [[Attach:usb-schematic.png|Attach:usb-schematic.png]]|'''USB Schematic'''
to:
%cframe text-align=center width=500% [[Attach:duousb-schematic.png|Attach:duusb-schematic.png]]|'''USB Schematic'''
Changed lines 100-101 from:
||RX||Input||FPGA Serial Receive (MISO)||N/A||N/A||P101||
||TX||Output||FPGA Serial Transmit (MOSI)||N/A||N/A||P105||
to:
||RX||Input||FPGA Serial Receive (MISO)||N/A||N/A||P46||
||TX||Output||FPGA Serial Transmit (MOSI)||N/A||N/A||P141||
Changed line 79 from:
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:duopower-callout.png
to:
%lframe width=200px bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:duopower-callout.png
Changed lines 87-89 from:
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:duousb-callout.png
The Papilio DUO uses the upgraded %newwin%[[http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232D.pdf|FT2232H]] dual channel USB chip. The FT2232H is an upgrade from the FT2232D used in previous Papilio boards. It has MPSSE on both channels and can achieve higher speeds.
to:
%lframe width=200px bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:duousb-callout.png
The Papilio DUO uses the upgraded %newwin%[[http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf|FT2232H]] dual channel USB chip. The FT2232H is an upgrade from the FT2232D used in previous Papilio boards. It has MPSSE on both channels and can achieve higher speeds.
Changed line 91 from:
*Channel B is connected to the Papilio Pro in an Asynchronous serial UART configuration that is capable of speeds up to 3MHz.
to:
*Channel B is connected to the Papilio DUO in an Asynchronous serial UART configuration that is capable of speeds up to 3MHz.
Changed line 79 from:
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:power-callout.png
to:
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:duopower-callout.png
Changed lines 87-91 from:
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:usb-callout.png
The Papilio Pro uses the same %newwin%[[http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232D.pdf|FT2232]] dual channel USB chip that the Papilio One does.

*Channel A is connected to the
Papilio Pro in an Asynchronous serial UART configuration that is capable of speeds up to 2MHz.
*Channel B is connected to the JTAG pins of the Papilio Pro and provides very fast programming of the FPGA (500mS).
to:
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:duousb-callout.png
The Papilio DUO uses the upgraded %newwin%[[http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232D.pdf|FT2232H]] dual channel USB chip. The FT2232H is an upgrade from the FT2232D used in previous Papilio boards. It has MPSSE on both channels and can achieve higher speeds.

*Channel A is connected to the JTAG pins of the Papilio DUO and provides very fast programming of the FPGA (500mS).
*Channel B is connected to the Papilio Pro in an Asynchronous serial UART configuration that is capable of speeds up to 3MHz
.
Deleted lines 92-95:

>>tip<<
The Papilio Pro includes a reset header (JP4) that can be populated with a jumper to hold the Spartan 6 FPGA in permanent reset mode. This frees up the JTAG Header to be used as an FT2232 JTAG/SPI/MPSSE Programmer.
>><<
Changed lines 80-82 from:
%rframe text-align=center height=220px% [[Attach:power-schematic.png|Attach:power-schematic.png]]|'''Power Schematic'''

One of the big improvements with the Papilio Pro is its power supply. The Spartan 6 simplifies the power requirements which allowed us to use a high efficiency %newwin%[[http://cds.linear.com/docs/Datasheet/3419fa.pdf|LTC3419]] switching power supply at about the same component cost as the Papilio One's power supply. The linear regulators used in the Papilio One would noticeably heat up when a complicated, high speed design, like the ZPUino, was running. With the Papilio Pro there is no detectable heat generated, even when the most demanding designs are running!
to:
%rframe text-align=center height=220px% [[Attach:duopower-schematic.png|Attach:duopower-schematic.png]]|'''Power Schematic'''

One of the big improvements with the Papilio DUO is its power supply. The Spartan 6 simplifies the power requirements which allowed us to use a high efficiency %newwin%[[http://cds.linear.com/docs/Datasheet/3419fa.pdf|LTC3419]] switching power supply at about the same component cost as the Papilio One's power supply. The linear regulators used in the Papilio One would noticeably heat up when a complicated, high speed design, like the ZPUino, was running. With the Papilio DUO there is no detectable heat generated, even when the most demanding designs are running!
Changed lines 47-48 from:
The Papilio Pro's %newwin%[[http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf|Spartan 6 FPGA]] offers some exciting new features over the Spartan 3:
to:
The Papilio DUO's %newwin%[[http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf|Spartan 6 FPGA]] offers some exciting features:
Changed line 53 from:
%rframe text-align=center width=200px% [[Attach:fpga_schematic.png|Attach:fpga_schematic.png]]|'''FPGA Schematic'''
to:
%rframe text-align=center width=200px% [[Attach:duofpga_schematic.png|Attach:duofpga_schematic.png]]|'''FPGA Schematic'''
Changed line 67 from:
||Papilio Pro||32||576Kbit (72KByte)||512Kbit (64KByte)||
to:
||Papilio DUO||32||576Kbit (72KByte)||512Kbit (64KByte)||
Added lines 1-258:
(:notabledit:)
(:include HardwareHeader:)

>>lrindent round frame float:right width:400px<<
'''Contents'''
[[<<]]
[[#Overview|Overview]][[<<]]
[[#PProFPGA|Spartan 6 LX9 FPGA]][[<<]]
[[#PProPower|Power]][[<<]]
[[#PProUSB|Dual Channel USB]][[<<]]
[[#PProSdram|SDRAM]][[<<]]
[[#PProSPIFlash|SPI Flash]][[<<]]
[[#PProIO|I/O]][[<<]]
[[#PProOscillator|Oscillator]][[<<]]
[[#PProJTAG|JTAG]][[<<]]
[[#PProReset|Reset]][[<<]]
[[#PProUserLED|User LED]][[<<]]
[[#PProLinks|Links]][[<<]]
[[#PProLicense|License]][[<<]]
[[#Images|Images]][[<<]]
>><<

[[#Overview]]
!!Papilio DUO
>>round frame<<
The Papilio DUO is an Open Source FPGA development board designed with the Arduino Mega footprint. It has a Spartan 6 FPGA on the top and an AVR Atmega32U4 (the same chip used in the Arduino Leonardo) on the bottom. It has 54 I/O lines, dual channel USB, integrated JTAG programmer, 512KB or 2MB of SRAM, and an efficient switching power supply.
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>>round frame float:left width:400px bgcolor=#ffffff<<
%width=500%[[Attach:duo.jpg|Attach:duo.jpg]]
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*Spartan 6 LX9 FPGA %newwin%([[http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf|Datasheet]])
*AVR ATmega32U4 Microcontroller %newwin%([[http://media.digikey.com/pdf/Data%20Sheets/Atmel%20PDFs/ATmega16U4,32U4.pdf|Datasheet]])
*High efficiency LTC3419 Step Down Dual Voltage Regulator %newwin%([[http://cds.linear.com/docs/en/datasheet/3419fa.pdf|Datasheet]])
*Dual Channel FTDI FT2232H USB 2.0 High Speed Interface %newwin%([[http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf|Datasheet]])
*512KB ISSI IS61WV5128BLL SRAM %newwin%([[http://www.issi.com/WW/pdf/61-64WV5128Axx-Bxx.pdf|Datasheet]]) OR 2MB ISSI IS61WV20488BLL SRAM %newwin%([[http://www.issi.com/WW/pdf/61-64WV20488.pdf|Datasheet]])
*64Mbit Macronix MX25L6445 SPI Flash %newwin%([[http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/3F21BAC2E121E17848257639003A3146/$File/MX25L6445E,%203V,%2064Mb,%20v1.8.pdf|Datasheet]])
*54 I/O pins arranged in a Arduino Mega form factor
*32Mhz Crystal Oscillator
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[[#PProFPGA]]
!!!Spartan 6 LX9 FPGA
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:fpga_callout.png
The Papilio Pro's %newwin%[[http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf|Spartan 6 FPGA]] offers some exciting new features over the Spartan 3:

'''Digital Signal Processing (DSP) Slices'''
->18 DSP48A1 Slices for DSP functions.
'''Clock Management Tile (CMT)'''
->The Papilio One (Spartan 3E) offered 4 Digital Clock Managers (DCM) but did not offer any Phase-Locked Loops (PLL). The Papilio Pro (Spartan 6) offers the more flexible CMT which provides both DCM's and PLL's!
%rframe text-align=center width=200px% [[Attach:fpga_schematic.png|Attach:fpga_schematic.png]]|'''FPGA Schematic'''
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\\

'''New I/O Standards'''
->The Papilio Pro (Spartan 6) has direct TMDS I/O support which means that DVI and HDMI interfaces can be implemented without any extra chips.
'''Multi-Boot Support'''
->You can load multiple bit files into the SPI Flash and setup the first bit file to select which one will be loaded. With some work we could make a ZPUino based bootloader that would have a VGA interface to choose which bit file to load.
'''BRAM Memory Blocks'''
->The Spartan 6 allows 18Kbit BRAM blocks to be split into two 9Kbit BRAM blocks.
->There is more built in SRAM - there is 64KByte of internal SRAM which is just enough to recreate the Commodore 64!

||class=prettytable3
||Papilio Board||18Kbit BRAM Blocks||Max SRAM||Usable SRAM||
||Papilio Pro||32||576Kbit (72KByte)||512Kbit (64KByte)||
||Papilio One 500K||20||360Kbit (45KByte)||320Kbit (40KByte)||
||Papilio One 250K||12||216Kbit (27KByte)||192Kbit (24KByte)
\\

>>important<<
BRAM's are 18Kbit in size including two parity bits. In most cases the two parity bits are not used so the BRAM's usable size becomes 16Kbit. If your design can use an 18 bit wide bus then it is possible to utilize the parity bits for data and gain access to all 18Kbit memory space.
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[[#PProPower]]
!!!Power
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:power-callout.png
%rframe text-align=center height=220px% [[Attach:power-schematic.png|Attach:power-schematic.png]]|'''Power Schematic'''

One of the big improvements with the Papilio Pro is its power supply. The Spartan 6 simplifies the power requirements which allowed us to use a high efficiency %newwin%[[http://cds.linear.com/docs/Datasheet/3419fa.pdf|LTC3419]] switching power supply at about the same component cost as the Papilio One's power supply. The linear regulators used in the Papilio One would noticeably heat up when a complicated, high speed design, like the ZPUino, was running. With the Papilio Pro there is no detectable heat generated, even when the most demanding designs are running!
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[[#PProUSB]]
!!!Dual Channel USB
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:usb-callout.png
The Papilio Pro uses the same %newwin%[[http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232D.pdf|FT2232]] dual channel USB chip that the Papilio One does.

*Channel A is connected to the Papilio Pro in an Asynchronous serial UART configuration that is capable of speeds up to 2MHz.
*Channel B is connected to the JTAG pins of the Papilio Pro and provides very fast programming of the FPGA (500mS).
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>>tip<<
The Papilio Pro includes a reset header (JP4) that can be populated with a jumper to hold the Spartan 6 FPGA in permanent reset mode. This frees up the JTAG Header to be used as an FT2232 JTAG/SPI/MPSSE Programmer.
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%cframe text-align=center width=500% [[Attach:usb-schematic.png|Attach:usb-schematic.png]]|'''USB Schematic'''
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|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio Pro Pin||
||RX||Input||FPGA Serial Receive (MISO)||N/A||N/A||P101||
||TX||Output||FPGA Serial Transmit (MOSI)||N/A||N/A||P105||
\\

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[[#PProSdram]]
!!!SDRAM
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:sdram-callout.png
%rframe height=300px% [[Attach:sdram-schematic.png|Attach:sdram-schematic.png]]
The Papilio Pro includes a 64Mbit Micron %newwin%[[http://download.micron.com/pdf/datasheets/dram/sdram/64MSDRAM.pdf|MT48LC4M16]] SDRAM chip. This additional SDRAM will open up a whole new breed of FPGA applications for the Papilio. The timing requirements and refresh signals of the SDRAM chip do make interfacing it more of a challenge than interfacing regular SRAM, or the internal BRAM. We are working on a SDRAM controller that you can drop into your designs so the SDRAM can be used like regular SRAM.

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!!!SDRAM Designs
*[[http://hamsterworks.co.nz/mediawiki/index.php/SDRAM_Memory_Controller|Hamster's SDRAM Controller]]
*[[https://github.com/alvieboy/ZPUino-HDL/blob/dcache/zpu/hdl/zpuino/boards/papilio-pro/S6LX9/sdram_hamster.vhd|Alvie's ZPUino SDRAM controller.]] (derived from Hamster's SDRAM controller).
*[[https://github.com/alvieboy/ZPUino-HDL/blob/dcache/zpu/hdl/zpuino/boards/papilio-pro/S6LX9/sdram_wrap.vhd|Wishbone wrapper for Alvie's SDRAM controller.]]
*[[http://www.xilinx.com/support/documentation/application_notes/xapp394.pdf|XAPP 394 Interfacing Mobile SDRAM with CPLD's.]]
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>>tip<<
The ZPUino Soft Processor includes a SDRAM controller which gives your ZPUino sketches 8MByte of code space!
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[[#PProSPIFlash]]
!!!SPI Flash
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:flash-callout.png
%rframe width=300px% [[Attach:flash-schematic.png|Attach:flash-schematic.png]]
The 64Mbit Macronix %newwin%[[http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/3F21BAC2E121E17848257639003A3146/$File/MX25L6445E,%203V,%2064Mb,%20v1.8.pdf|MX25L6445]] SPI Flash chip is the largest ever included with a Papilio FPGA. It is the largest available in the 8-SOIC footprint, and is included for good reason! The new multi-boot feature of the Spartan 6 means we can put as many FPGA bit files on the SPI Flash as will fit and use a "golden image" to select which one will boot at startup. Spartan 6 LX9 bit files are 333KBytes in size which means that the Papilio Pro can save up to 23 bit files in SPI Flash. Or, we can save and retrieve user data using techniques like the SmallFS filesystem or [[http://www.papilio.cc/index.php?n=Playground.Bootstrap|bootstrap code]] that loads data from SPI Flash to SRAM at startup.
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|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio Pro Pin||
||FLASH_CS||Output||SPI Flash Chip Select||N/A||N/A||P38||
||FLASH_CLK||Output||SPI Flash Clock||N/A||N/A||P70||
||FLASH_MOSI||Output||SPI Flash Master Out Slave In (MOSI)||N/A||N/A||P64||
||FLASH_MISO||Input||SPI Flash Master In Slave Out (MISO)||N/A||N/A||P65||
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[[#PProIO]]
!!!I/O
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:io-callout.png
%rframe height=250px% [[Attach:io-schematic.png|Attach:io-schematic.png]]
The I/O of the Papilio Pro is backwards compatible with the Papilio One, all existing Papilio Wings and MegaWings work with the Papilio Pro.

The major difference between the Papilio Pro and Papilio One with respect to User I/O is the available voltage levels. The Papilio Pro sets all I/O voltage pins to 3.3V while the Papilio One can switch between 1.2V, 2.5V, and 3.3V. This was a seldom used feature that was dropped in the Papilio Pro for greater compatibility. Additionally, the Papilio Pro does not provide a 2.5V power rail, the 2.5V pin on the Wing Header is left unconnected. There are no Wings or MegaWings that use 2.5V power and there probably never will be... 3.3V seems to be the defacto standard for current peripherals.
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[[#PProOscillator]]
!!!Oscillator
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:osc-callout.png
%rframe width=300px% [[Attach:osc-schematic.png|Attach:osc-schematic.png]]
The Papilio Pro has a 32Mhz oscillator that can be converted to any speed desired inside the FPGA using the Clock Management Tile (CMT). There are two PLLs and two [[http://www.papilio.cc/index.php?n=Papilio.DigitalClockManager|Digital Clock Managers (DCM)]] available for your designs.
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|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio Pro Pin||
||CLK||Input||External 32Mhz Oscillator||N/A||N/A||P94||
\\

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[[#PProJTAG]]
!!!JTAG
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:jtag-callout.png
%rframe width=200px% [[Attach:jtag-schematic.png|Attach:jtag-schematic.png]]
The JTAG header on the Papilio Pro is provided for a couple different reasons:

'''Use a Xilinx Programming Cable'''
->If you want to use the Xilinx tools such as EDK, Chipscope, or Impact with the Papilio you need a way to use a Xilinx programming cable. The Papilio has a Xilinx JTAG header but the problem is that in the default mode the FT2232D USB chip is connected to the JTAG pins and interferes with programming. What is needed is to put the FT2232 into a mode where the JTAG pins go into High-Z leaving the Xilinx JTAG pins free for the programming cable. To learn more about using a Xilinx Programming Cable visit the [[http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/xilinx-programming-cable-with-papilio-r39|original forum post]] or [[http://www.gadgetfactory.net/2012/09/use-a-xilinx-programming-cable-with-the-papilio/|blog post]].

'''Bypass the FPGA and use the FT2232 as a JTAG/SPI/MPSSE Programmer'''
->The Papilio Pro provides the JP4 pin header, jumping this header will hold the Spartan 6 FPGA in a reset state which frees up the JTAG pins to be controlled by the FT2232. OpenOCD, FlashRAM, and any other FT2232 based software should work directly with this method.

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|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio Pro Pin||
||JTAG_TMS||Input||JTAG TMS||N/A||N/A||P107||
||JTAG_TCK||Input||JTAG TCK||N/A||N/A||P109||
||JTAG_SI||Input||JTAG SI||N/A||N/A||P64||
||JTAG_SO||Output||JTAG SO||N/A||N/A||P65||
\\

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[[#PProReset]]
!!!Reset
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:reset-callout.png
%rframe width=300px% [[Attach:reset-schematic.png|Attach:reset-schematic.png]]
Pressing the reset button will cause the Spartan 6 FPGA to do a hard reset and reload the first bit file from SPI Flash. This is a pretty drastic measure that will wipe out anything running on the FPGA. In most cases it is more desirable to utilize a user button to perform a reset within your design that just initializes all registers to zero.
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|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio Pro Pin||
||RESET||Input||FPGA Reset||N/A||N/A||P37||
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[[#PProUserLED]]
!!!User LED
%lframe bgcolor=#c5d7dd border='1px solid #429ae0'% Attach:led-callout.png
%rframe height=100px% [[Attach:led-schematic.png|Attach:led-schematic.png]]
The Papilio Pro provides one user LED that is connected directly to the Spartan 6 FPGA. It is not shared with any of the I/O pins and can be controlled directly from your VHDL or sketches.
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|| class=prettytable2
||Name||Direction (FPGA Perspective)||Function||Arduino Pin||Papilio Wing Pin||Papilio Pro Pin||
||LED1||Output||USER LED1||N/A||N/A||P112||
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[[#PProLinks]]
!!!Links
(:include Papilio.PapilioProLinks :)
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[[#PProLicense]]
!!!License
(:div style='text-align:center; background:#dddddd; border:1px solid #000000; width:100%; padding:5px;':)
%center%[[http://creativecommons.org/licenses/by-nc-sa/3.0/|http://i.creativecommons.org/l/by-nc-sa/3.0/88x31.png]]
Papilio Pro is licensed under a [[http://creativecommons.org/licenses/by-nc-sa/3.0/|Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License]].
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Papilio Pro copyright Jack Gassett, Gadget Factory.
(:divend:)
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[[#Images]]
!!!Images
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0' newwin% [[Attach:Papilio pro.png|Attach:Papilio pro.png]]
%lframe width=240 bgcolor=#c5d7dd border='1px solid #429ae0' newwin% [[Attach:papilio pro2.png|Attach:papilio pro2.png]]
>>postit<<
%notetitle% Papilio Pro%%

Click the images for full size hi-resolution views of the Papilio Pro.
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%lframe height=700 width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[https://github.com/GadgetFactory/Papilio-Pro/blob/master/BPC3010_Papilio_Pro.pdf?raw=truee|Attach:ppro-schematic.png]]
>>postit<<
%notetitle% Papilio Pro Schematic%%

Click the image to load a PDF version of the Papilio Pro Schematic
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%lframe width=500 bgcolor=#c5d7dd border='1px solid #429ae0'% [[Attach:ppro-assembly.png|Attach:ppro-assembly.png]]
>>postit<<
%notetitle% Assembly View%%

Click the image for a full size view of the boards part layout.
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