Xilinx VHDL UART Example

Here is a three part screencast that provides an example of implementing a high speed 3Mb/s UART with the Papilio One board and the FT2232 USB chip.

 

The project uses the free Xilinx VHDL UART example because it is optimized for Xilinx hardware, it provides the smallest and fastest UART possible. The source code requires an end user license agreement which prevents us from providing the source code. Part one of the video tutorial walks you through adding the source code to the project after it has been downloaded from Xilinx.

Part 1

http://youtu.be/Hwq0mF0SxOM

Links:

Download the Example project from Gadget Factory.

Xilinx App Note. XAPP223

Download Picoblaze source code.

Please click the link to view the rest of the videos.

Part 2

http://youtu.be/it1ZkYTsjzE

Part 3

http://youtu.be/6TayUD7XAsE

Followup – Changing the ISE project for use with the Papilio One 500K board


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10 Responses to “Xilinx VHDL UART Example”

  1. texane says:

    hi Jack,

    I finally got time to test the papilio 500k. The basic bitstream in papilioloader works (the one sending the ascii
    table to serial port). But I cannot manage to make the above tutorial work. I compiled the code and change the settings to make it work for the 500k version… but cannot get anything echoed from minicom (set baudrate to 3mbauds). Is there something to change?

    Thanks for helping,

    Fabien.

    • texane says:

      I forgot to mention I use the following command line: papilio_loader -f file.bit -v …

    • Jack Gassett says:

      Hello,

      I should have thought about the 500k version! Sorry about that, what you did sounds like it should work but I’m going to put on my task list an item to follow up with this. I will get the code working on the 500k board and make a followup video for it.

      Jack.

      • texane says:

        Thanks for replying. I will have a deeper look and will keep you informed if I manage to make it work.
        Regards,

        Fabien.

        • texane says:

          And could it be possible to have the source of ASCIITable_Quickstart-Papilio_One_500K.bit so that I can regenerate it and check if the problem does not come from the webise version I am using?

          my email:
          fabien.lementec@gmail.com

          thanks,

          fabien.

          • Jack Gassett says:

            Hello Fabien,

            The ASCIITable example is a sketch that runs on the AVR8 processor. So you can look at the VHDL source for the AVR8 processor but there is no “source” I can give you for the ASCIITable_Quickstart example. It is a combination of C code that gets merged into the bitstream along with the AVR8 and is a dynamic bitstream.

            Jack.

  2. Jack Gassett says:

    This post has been updated with a followup screencast that shows what steps need to be taken to make it work on the Papilio One 500K board.

    Jack.

  3. gaurav34 says:

    hey, i wanna try it with xiling spartan 3-e board..please send me the ucf for spartan3-e for the uart..

  4. gaurav34 says:

    hey, i wanna try it with xiling spartan 3-e xc3s500e board..please send me the ucf..my email id is raopappu@rocketmail.com

  5. Miem says:

    Hello,
    I am new to FPGAs and to the Papilio boards.
    As you may know Arduino Mega has 4 UARTs. If we try to emulate super version of Arduino Mega on Papilio board, how many UARTs a Papilio board can have? (i.e. can we have more than 4 UARs on Papilio?)

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