Papilio.GettingStartedISE History

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>>warning<<
When downloading from Xilinx the default page will be for the Vivado Design Tools. Be sure to change to ISE Design Tools and download the latest ISE Design Suite.
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>>warning<<
If you are running 64bit Windows 8 you will run into a bug that will prevent you from loading a license file or opening any projects. [[http://www.gadgetfactory.net/2013/09/having-problems-installing-xilinx-ise-on-windows-8-64bit-here-is-a-fix-video-included/|Visit this page for a fix.]]
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May 02, 2013, at 09:49 AM by Jack Gassett -
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(:input checkbox color white:)Put a check mark in “Allow Unmatched LOC Contratints”
to:
(:input checkbox color white:)Put a check mark in “Allow Unmatched LOC Constraints”
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>>warning<<
Be careful with this setting, it can mask problems such as a typo in your ucf file as [[http://forum.gadgetfactory.net/index.php?/topic/1622-papilio-pro-logic-wing-vga-pins/|illustrated here]]. The safest practice is to comment out unused lines from your ucf file.
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April 16, 2013, at 12:04 PM by Jack Gassett -
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!!Papilio Xilinx ISE WebPack VHDL Getting Started
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'''Contents'''
[[<<]]
[[#Overview|Overview]][[<<]]
[[#Section1|Prerequisites]][[<<]]
[[#Section2|Start New Project]][[<<]]
[[#Section3|Import Example Code]][[<<]]
[[#Section4|Synthesize the Design]][[<<]]
[[#Section5|Load Bit File]][[<<]]
[[#Section6|Verify it Works]][[<<]]
[[#Section7|What's Next?]][[<<]]
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[[#Overview]]
!!Papilio Xilinx ISE WebPack VHDL Getting Started
>>round frame<<
Welcome to the Webpack VHDL Quickstart Guide for the Papilio Platform. This guide shows how to get a simple VHDL design up and running on the Papilio Hardware. It will cover using Xilinx Webpack to create a project, import a constraint file, synthesize a design, and load the generated bit file to the Papilio Hardware.
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>>round frame float
:left width:800px bgcolor=#ffffff<<
%width=500%[[Attach:product image.jpg|Attach:product image.jpg]]
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[[<<]]

>>round frame<<
!!!Quick Links
-> [[http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html|Xilinx ISE Design Suite Software Download]]
--> This is what you need to download to write VHDL or Verilog code for the Papilio.
-> [[http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_5/irn.pdf|Xilinx ISE Design Suite Official Installation Guide]]
--> Have questions about the install process, get help straight from Xilinx.
-> [[http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_5/ise_tutorial_ug695.pdf|Xilinx ISE Design Suite In-Depth Tutorial]]
--> This Quickstart Guide for the Papilio will get you started, if you want to learn more read this full guide from Xilinx.
-> [[https://github.com/GadgetFactory/VHDL_Example_Code/tree/master/WebPack_QuickStart|Full source code for this example on GitHub.]]
-> When you complete this simple VHDL example start learning more with the following resources:
--> [[http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/logicstart-megawing/intro-to-spartan-fpga-ebook-r34|Hamster’s Free VHDL eBook]] - Designed to be used with the [[http://store.gadgetfactory.net/logicstart-megawing/|LogicStart MegaWing]].
--> [[http://hamsterworks.co.nz/mediawiki/index.php/FPGA_course|Hamster’s Wiki]]
--> [[http://www.freerangefactory.org/site/pmwiki.php/Main/Books|Free Range VHDL eBook]]

!!!Operating Systems
-> Windows Vista
-> Windows XP
-> Windows 7
-> Windows 8

!!!Hardware this Guide Applies to:
-> [[http://store.gadgetfactory.net/papilio-one-250k/|Papilio One 250K]]
-> [[http://store.gadgetfactory.net/papilio-one-500k/|Papilio One 500K]]
-> [[http://store.gadgetfactory.net/papilio-pro/|Papilio Pro LX9]]
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[[<<]]
----
[[#Section1]]
!!!Prerequisites

If this is the first time using the Papilio hardware then please take a moment to go through the [[Papilio.GettingStarted|Papilio Quickstart Guide]] to install the drivers, Papilio Loader, and to get the file associations setup.
Then, download and install the Xilinx ISE Design Suite software. During the install choose, “'''ISE WebPack'''” as your product to install.
-> [[http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html|Xilinx ISE Design Suite Software Download]]
--> This is what you need to download to write VHDL or Verilog code for the Papilio.
-> [[http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_5/irn.pdf|Xilinx ISE Design Suite Official Installation Guide]]
--> Have questions about the install process, get help straight from Xilinx.
-> [[http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_5/ise_tutorial_ug695.pdf|Xilinx ISE Design Suite In-Depth Tutorial]]
--> This Quickstart Guide for the Papilio will get you started, if you want to learn more read this full guide from Xilinx.
-> [[https://github.com/GadgetFactory/VHDL_Example_Code/tree/master/WebPack_QuickStart|Full source code for this example on GitHub.]]

----
[[#Section2]]
!!!Start a New Project in Xilinx Project Navigator

%rframe text-align=center width=400px% [[Attach:img1.jpg|Attach:img1.jpg]]
(:input checkbox color white:
) Start Xilinx Project Navigator\\
(:input checkbox color white:) Click on “New Project”
[[<<]]

%rframe text-align=center width=400px% [[Attach:img2.jpg|Attach:img2.jpg]]
(:input checkbox color white:) Type in the name “Webpack_Quickstart”, choose a location, and press “Next”.
[[<<]]

%rframe text-align=center width=400px% [[Attach:img3.jpg|Attach:img3.jpg]]
(:input checkbox color white:) Make sure all settings match the screenshot below with the following exceptions:
* For the 500K Papilio boards select “SC3S500E” instead.
* For the Papilio Pro change:
** Family to “Spartan6"
** Device to “XC6SLX9"
** Package to “TQG144"
** Speed to "-2"
(:input checkbox color white:)Press "Next"
[[<<]]

%rframe text-align=center width=400px% [[Attach:img4.jpg|Attach:img4.jpg]]
(:input checkbox color white:) Click “New Source”\\
(:input checkbox color white:) Select “VHDL Module” and type in a filename of Webpack_Quickstart, press “Next”. \\
(:input checkbox color white:) Press “Next” on the Define Module window without entering anything. Press “Finish”.\\
(:input checkbox color white:) Press “Next” on the Create New Source Window.\\
[[<<]]

%rframe text-align=center width=400px% [[Attach:img5.jpg|Attach:img5.jpg]]
(:input checkbox color white:) Download the User Constraint File (ucf) for your board from the [[http://forum.gadgetfactory.net/index.php?/files/|Gadget Factory Downloads]] section.
*[[http://forum.gadgetfactory.net/index.php?/files/file/2-papilio-one-generic-ucf/|For Papilio One 250K and 500K.]]
*[[http://forum.gadgetfactory.net/index.php?/files/file/4-papilio-pro-generic-ucf/|For Papilio Pro LX9.]]
(:input checkbox color white:) Click “Add Source” in the Add Existing Sources window. Browse to the downloaded ucf file.\\
(:input checkbox color white:) Make sure “Copy to Project” is selected, press “Next”\\
(:input checkbox color white:) Press "Finish"\\
[[<<]]\\


----
[[#Section3]]
!!!Import Example Code into the Project
%rframe text-align=center width=400px% [[Attach:img6.jpg|Attach:img6.jpg]]
(:input checkbox color white:)Double click on “Webpack_Quickstart” in the Hierarchy pane to open the vhdl file.\\
(:input checkbox color white:)Replace the entire contents of the “Webpack_Quickstart.vhd” file with the following example code.

>>lrindent round frame<<
(:source lang=vhdl :)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity WebPack_QuickStart is
Port ( A : out STD_LOGIC_VECTOR (15 downto 0);
B : out STD_LOGIC_VECTOR (15 downto 0);
C : out STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC);
end WebPack_QuickStart;

architecture Behavioral of WebPack_QuickStart is
signal counter : STD_LOGIC_VECTOR(47 downto 0) := (others => '0');
begin
--Counter to drive blinking pins
count: process(clk)
begin
if rising_edge(clk) then
counter <= counter+1;
end if;
end process;
--Pins are connected to the counter to cause blinking at varying frequencies
A <= counter(35 downto 20);
B <= counter(31 downto 16);
C <= counter(15 downto 0);
end Behavioral;
(:sourcend:)
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----
[[#Section4]]
!!!Synthesize the Design
We have a slight problem with the UCF files that we downloaded that we need to take care of before we proceed. The generic UCF files have more pins defined then we are using with this project, the default settings for WebPack will generate an error when this happens. We need to change the settings so those extra pins are ignored.

%rframe text-align=center width=400px% [[Attach:img11.png|Attach:img11.png]]
(:input checkbox color white:)Right click “Translate” under Implement Design and select “Process Properties”
[[<<]]

%rframe text-align=center width=400px% [[Attach:img12.png|Attach:img12.png]]
(:input checkbox color white:)Put a check mark in “Allow Unmatched LOC Contratints”
[[<<]]

%rframe text-align=center width=400px% [[Attach:img13.png|Attach:img13.png]]
You will also have to open the ucf file and comment out any lines that have a PULLUP defined. \\
(:input checkbox color white:) Highlight the ucf file, expand User Constraints and double click on “Edit Constraints (Text)"
[[<<]]

%rframe text-align=center width=400px% [[Attach:img14.png|Attach:img14.png]]
(:input checkbox color white:)Comment out any lines with a PULLUP defined.
[[<<]]

%rframe text-align=center width=400px% [[Attach:img15.jpg|Attach:img15.jpg]]
(:input checkbox color white:)Double click “Generate Programming File” under the Processes pane.
[[<<]]

----
[[#Section5]]
!!!Load the synthesized bit file to the Papilio board
Xilinx does not provide any method for 3rd parties to use the built in programming tools so it is necessary to use the Butterfly Loader to load the generated bit file.

%rframe text-align=center width=400px% [[Attach:img16.jpg|Attach:img16.jpg]]
(:input checkbox color white:) Navigate to the directory where the project was created and locate the “webpack_quickstart.bit” file. Verify that the timestamp looks correct. \\
(:input checkbox color white:) Ensure that the Papilio board is plugged into the USB port.\\
(:input checkbox color white:) Double click on the generated bit file to program directly to the FPGA or right click on the bit file to choose other options such as writing to SPI Flash.
[[<<]]

----
[[#Section6]]
!!!Verify that the design works as expected
The example code simply connects an incrementing timer to the
I/O pins of the Papilio board. The end result is that connecting a Button/LED Wing to the various Wing Slots will show blinking LED’s at various frequencies. If no Button/LED Wing is available then just connect a multimeter to the I/O pins and observe voltage falling and rising.

----
[[#Section7]]
!!!What's Next
When you complete this simple VHDL example start learning more with the following resources:
-> [[http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/logicstart-megawing/intro-to-spartan-fpga-ebook-r34|Hamster’s Free VHDL eBook]] (Designed to be used with the [[http://store.gadgetfactory.net/logicstart-megawing/|LogicStart MegaWing]].)
-> [[http://hamsterworks.co.nz/mediawiki/index.php/FPGA_course|Hamster’s Wiki]]
-> [[http://www.freerangefactory.org/site/pmwiki.php/Main/Books|Free Range VHDL eBook]]
April 11, 2013, at 05:43 PM by Jack Gassett -
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(:title Papilio platform - Getting Started WebPack VHDL:)

(:keywords FPGA, Xilinx, Papilio platform, Firefly platform, Wings, FPGA development, electronics, FPGA India, embedded processors, open source hardware, configurable logic:)

(:description Papilio platform is easy to use FPGA and microcontroller development platform for beginners and a powerful modular design environment for professional developers:)

(:include GettingStartedHeader:)

>>lrindent round frame text-align=center<<
!!Papilio Xilinx ISE WebPack VHDL Getting Started
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