DCM (Digital Clock Manager) Tutorial

One of the killer features of the Xilinx FPGA’s used in the Papilio Boards are the DCM’s (Digital Clock Manager). The DCM’s allow you to take the incoming 32Mhz clock from the external oscillator and generate any speed clock that you want! Even better, you get four DCM’s so you can generate four completely independent clocks all running at whatever frequency you desire. The DCM’s are so powerful they can even be used as the base for a nice frequency generator as outlined in this reference design by Ken Chapman.

 

Many open source designs on the Internet have been written for evaluation boards that use an external 50Mhz clock, but a 50 Mhz clock is right on the edge of what is considered a high speed design. The Papilio One purposely uses a slower 32Mhz clock that is not considered high speed and is better suited for a double layer circuit board. It makes sense to keep high speed signals inside the FPGA and off the circuit board when possible. This tutorial shows how to convert the 32Mhz clock to the required 50Mhz clock and keep the high speed 50Mhz clock internal to the FPGA which sidesteps any high speed Signal Integrity issues such as reflection, crosstalk, or ringing.

 

PART 1

http://youtu.be/PYgrCGD_Pqs

 

PART 2


http://youtu.be/W63Z9ix2aak

 

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3 Responses to “DCM (Digital Clock Manager) Tutorial”

  1. Oldsirhippy says:

    Many thanks for these brilliant videos – prior to finding the videos I spent a number of days figuring out how to use the code the DCM wizard generated. I eventually got it and ISE gave me green ticks. I only discovered your tutorial afterwards and it clearly explained what to do! I wish I had searched your site more thoroughly before…
    Best wishes.

  2. Jack Gassett says:

    Thank you! I’m glad to hear it is helpful.

    Jack.

  3. YvesMcDonald says:

    Brilliant indeed! I was starting to wonder how to uses some of the good features of my Spartan3E FPGA. Your videos were up to the point. I think the same procedure could apply to other core features (multipliers and memory)and IP (lots of cool stuff there too!).

    One remark: I use the free edition of PlanAhead V13.x for Linux and I could not generate DCM VHDL code with it. However, it is still possible to generate the code elsewhere – by using the coregen utility. Coregen has a graphical user interface which let the user specify the target chip, configure and generate code for the desired feature(s). Graphics looks a bit outdated (X11 widget for 1990′s :-) ), but it works! No major complaints so far: a very handy tool.

    Thanks for the videos, well done!

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