How-to debug internal FPGA Logic with the $50 Openbench Logic Sniffer.

This tutorial shows how to use the $50 OpenBench Logic Sniffer to debug internal FPGA logic. Debugging internal FPGA logic can be pretty challenging and time consuming, a lot can be done using simulation but when you have logic that interacts with the outside world debugging can come to a grinding halt. The traditional solution is to use the $500+ Chipscope Pro software, but for many this is just too expensive. This tutorial shows a cheap and effective way to get a look at what is going on inside your FPGA.

 

The FPGA development board used in the screencast is Gadget Factories Open Source Papilio One board. Think of the Papilio One as the “Arduino” of FPGA development boards.

 

Part 1

Introduction, overview, and background information.

 

Part 2

  • Quick overview of the UART states.
  • A look at the Papilio ucf file and the Logic Sniffer project ucf file.
  • Determining which external pins are free.
  • Opening the Xilinx FPGA editor.
  • Using probes to connect internal Logic/Nets to external pins.

 

Part 3

  • Continued – Using probes to connect internal Logic/Nets to external pins.
  • Generate probed bitstream file.
  • Load probed bitstream to the Papilio One FPGA development board.
  • Setting up the OpenBench Logic Sniffer for data capture.

 

Part 4

  • Continued – Setting up the OpenBench Logic Sniffer for data capture.
  • Updating channel diagram names.
  • Generating and capturing test data.
  • Doing sanity check to verify the captured data matches the generated data.
  • Comparing captured data to VHDL source code.

 

Part 5

  • Continued – Comparing captured data to VHDL source code.
  • Conclusions

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